5222-DS00-R datasheet(49/76 Pages) BOARDCOM

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Preliminary Data Sheet

BCM5222

7/20/04

Broadcom Corporation

Document 5222-DS02-405-R

Auxiliary Mode 2 Register

Page 37

10BT DRIBBLE BIT CORRECT

When enabled, the PHY rounds down to the nearest nibble when dribble bits are present on the 10Base-T input stream.

JUMBO PACKET ENABLE

Writing a 1 to this bit enables jumbo sized packets to be received and transmitted.

TXC INVERT

Writing a 1 to bit 8 of the Auxiliary Mode 2 register will invert the TXC clock.

BLOCK 10BT ECHO MODE

When enabled, during 10BASE-T half-duplex transmit operation, the TXEN signal does not echo onto the RXDV pin. The

TXEN echoes onto the CRS pin and the CRS deassertion directly follows the TXEN deassertion.

QUALIFIED PARALLEL DETECT MODE

This bit allows the auto-negotiation/parallel detection process to be qualified with information in the Advertisement register.

If this bit is not set, the local BCM5222 device is enabled to Auto-Negotiate. If the far-end device is a 10BASE-T or 100BASE-

TX non-Auto-Negotiating legacy type, the local device Auto-Negotiate/Parallel detects the far-end device, regardless of the

Advertisement register (04h) contents.

If this bit is set, the local device compares the link speed detected to the contents of its Advertisement register. If the

particular link speed is enabled in the Advertisement register, the local device asserts link. If the link speed is disabled in this

Reserved

R/W

Write as 1, Ignore when read

Reserved

R/W

Write as 0, Ignore when read

Qual Parallel Detect Mode

R/W

1 = Enable, 0 = Disable

Reserved

Ignore when read

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after

read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

Table 22: Auxiliary Mode 2 Register (Address 27d, 1Bh)

BIt

Name

R/W

Description

Default

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