Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

5222-DS00-R Scheda tecnica(PDF) 21 Page - Broadcom Corporation.

Il numero della parte 5222-DS00-R
Spiegazioni elettronici  Dual Port 10/100BASE-TX IEEE 802.3u Fast Ethernet Transceiver
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  BOARDCOM [Broadcom Corporation.]
Homepage  http://www.broadcom.com
Logo BOARDCOM - Broadcom Corporation.

5222-DS00-R Scheda tecnica(HTML) 21 Page - Broadcom Corporation.

Back Button 5222-DS00-R Datasheet HTML 17Page - Broadcom Corporation. 5222-DS00-R Datasheet HTML 18Page - Broadcom Corporation. 5222-DS00-R Datasheet HTML 19Page - Broadcom Corporation. 5222-DS00-R Datasheet HTML 20Page - Broadcom Corporation. 5222-DS00-R Datasheet HTML 21Page - Broadcom Corporation. 5222-DS00-R Datasheet HTML 22Page - Broadcom Corporation. 5222-DS00-R Datasheet HTML 23Page - Broadcom Corporation. 5222-DS00-R Datasheet HTML 24Page - Broadcom Corporation. 5222-DS00-R Datasheet HTML 25Page - Broadcom Corporation. Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 76 page
background image
Preliminary Data Sheet
BCM5222
7/20/04
Broadcom Corporation
Document 5222-DS02-405-R
Hardware Signal Definitions
Page 9
E10
65
TMS/TXER{1}
IPD
Test Mode Select. This pin becomes TMS if TRST is high.
Single control input to the JTAG TAP controller is used to
traverse the test-logic state machine. Sampled on the rising
edge of TCK.
F9
64
TDO/PAUSE{1}
O3S
Test Data Output. This pin becomes TDO if TRST is high.
Serial data output from the JTAG TAP controller. Updated on
the falling edge of TCK.
POWER
B8, C4
99, 82
DVDD
PWR
Digital VDD (1.8V). Connect these pins to decoupling
capacitors as shown in Figure 17 on page 60.
J5
41
AVDD
PWR
Analog VDD (1.8V). Connect this pin to decoupling
capacitors as shown in Figure 17 on page 60.
B3, C8,
D1, E8,
G1, H10
1, 11,
22, 56,
70, 80
OVDD
PWR
3.3V Digital Periphery (Output Buffer) VDD supply.
B6, B4,
B9
100, 90,
81
DGND
GND
Digital Ground.
G5, J6,
H5, H6
39, 40,
42, 43
AGND
GND
Analog Ground.
J2
28
BIASVDD
PWR
BIAS VDD (3.3V). Connect this pin to decoupling capacitors
as shown in Figure 17 on page 60.
J3
30
BIASGND
GND
Bias Ground. Connect this pin to AGND.
H7, H1,
D2, E9
12, 23,
55, 69
OGND
GND
Output Buffer Ground. Digital Periphery (Output Buffer)
ground.
J4
34
PLLAGND
GND
PLL Analog Ground. Phase Locked Loop ground.
K1
31
PLLAVDD
PWR
PLL Analog VDD (1.8V). 1.8V, Phase Locked Loop VDD
Core. Connect this pin to decoupling capacitors as shown in
Figure 17 on page 60.
NO CONNECTS
J8, J9
G3, F10
26, 48,
49, 61
NC
NC
No Connection. Leave these pins floating.
Table 3: Pin Descriptions (Cont.)
BGA
MQFP
Pin Label
Type
Description
[MSB:LSB]; OVERLINE = active-low signal, I = input, O = output, I/O = bidirectional, IPU = input w/ internal pull-up, OOD
= open-drain output, O3S = three-state output, B = Bias, PWR = power supply, GND = ground



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com