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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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BT8376EPF Scheda tecnica(PDF) 67 Page - Synaptics Incorporated. |
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BT8376EPF Scheda tecnica(HTML) 67 Page - Synaptics Incorporated. |
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67 / 323 page  Bt8370/8375/8376 2.0 Circuit Description Fully Integrated T1/E1 Framer and Line Interface 2.6 Clock Rate Adapter N8370DSE Conexant 2-39 2.6 Clock Rate Adapter The full function Clock Rate Adapter is included in all Bt8370 and Bt8375 devices. In the Bt8376, the CLADO output is not implemented. The Clock Rate Adapter (CLAD) illustrated in Figures 2-21 and 2-22 uses an input clock reference at a particular frequency (range 8 kHz to 16,384 kHz) to synthesize an output clock (CLADO and JCLK) at a different frequency (range 1024 kHz to 16,384 kHz). The CLAD also controls the read or write pointers of the elastic store by synthesizing a Jitter-attenuated Line rate Clock (JCLK); thus, it is an integral part of the Jitter Attenuator (JAT). The CLAD input clock jitter tolerance and jitter transfer functions are illustrated in Figures 2-9 and 2-10. These diagrams are illustrated for various programmed loop filter gain values (LFGAIN; addr 090). |
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