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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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BT8376EPF Scheda tecnica(PDF) 243 Page - Synaptics Incorporated. |
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BT8376EPF Scheda tecnica(HTML) 243 Page - Synaptics Incorporated. |
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243 / 323 page  Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface 3.17 System Bus Registers N8370DSE Conexant 3-125 RFSLIP Controlled RSLIP Event—RUSLIP and RFSLIP event status are latched active-high when receive slip error is detected. Either event reports RSLIP error in ISR5 [addr 006]. Active-high hold interval is defined by LATCH_ERR [addr 046]. Two types of errors are detected: 1. FSLIP = Controlled ±1 frame slip on RPCMO data output. FSLIP affects RPCMO, but does not change the alignment of system bus RFSYNC or RMSYNC signals. 2. USLIP = Uncontrolled ±1 to ±256 bit slip on RPCMO. USLIP affects both system bus data and sync outputs. RUSLIP and RFSLIP status depends on the receive system bus configuration [RSB_CR; addr 0D1]. RUSLIP Uncontrolled RSLIP Event—See RFSLIP description. RSBI Mode RUSLIP RFSLIP RSLIP Event Notes Normal 0 0 none — 0 1 FSLIP Most recent slip error direction is reported in RSDIR. 1 0 USLIP An uncontrolled slip can occur in Normal mode due to a resync of the SBI or, in T1 rate converted applications, the active time slots are reassigned. The former sets RSDIR = 0; the latter sets RSDIR = 1. Short 0 0 none — 0 1 FSLIP — 1 0 USLIP In Short-Delay mode, if the bus clock is faster than receive clock, the system bus resynchronizes and USLIP is reported. If the receive clock is faster, RSLIP reverts to Normal mode and reports FSLIP errors. Elastic 0 0 none — 1 0 USLIP RFSLIP is not applicable (read zero value) while the RSLIP buffer is bypassed or configured as elastic store. FSLIP or USLIP errors reported upon Bypass mode initialization should be ignored. Bypass —— — — |
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