SMM205

Preliminary Information

Summit Microelectronics, Inc

2069 1.4 6/23/03

9

STATUS REGISTER

A status register exists for I

the COMP1 and COMP2 inputs.

Two bits in this

status register reflect the current state of the inputs (1

= fault, 0 = no fault). Two additional bits show the

state of the inputs latched by one of two events

programmed in the configuration.

The first event

option is the FAULT# output going active. The second

event option is the READY pin going low. The READY

pin is an I/O. As an output the READY output pin

goes active when the DC controlled voltages are at

their set point. As an input programmed to active high

it can be pulled low externally and latch the state of

the COMP inputs. This second event option allows

the state of the COMP inputs on multiple devices to be

latched at the same time while a host monitors their

FAULT# outputs.

MARGINING

The SMM205 has two additional Active DC Output

Control voltage settings: margin high and margin low.

The margin high and margin low settings can be as

much as

±10% of the nominal setting depending on

the manufacturer.

The SMM205 range can be as

large as VREF_CNTL to VDD. These settings are

stored in the configuration registers and are loaded

into the Active DC Output Control voltage setting by

margin commands issued via the I

must be enabled for Active DC Output Control in order

to enable margining.

The margin command registers contain two bits that

decode the commands to margin high, to margin low,

or to control to the nominal setting. Once the SMM205

receives the command to margin the supply voltage it

begins adjusting the supply voltage to move toward

the desired setting.

When this voltage setting is

reached a bit is set in the margin status registers and

the READY signal becomes active.

margining.

WRITE PROTECTION

Write protection for the SMM205 is located in a volatile

register where the power-on state is defaulted to write

protect. There are separate write protect modes for

the configuration registers and memory. In order to

write protection register. Other codes will also enable

writes to the configuration register but not to the

memory but not to the configuration registers. The

SMM205 also features a Write Protect pin (WP#)

which, when asserted, prevents writing to the

configuration registers and EE memory. In addition to

these two forms of write protection there is also a

configuration

register

lock

bit

which,

once

programmed, does not allow the configuration

registers to be changed.

Figure 5 – SMM205 margin example. The nominal setting for channel 1 and 2 is 2.5V and 1.8V. The device

margins the DC/DC converters from nominal to high (2.8V and 2.1) then to nominal, then to low (2.3V and

1.5V), then to nominal, then to channel 1 high and channel 2 low, and then back to nominal. The READY

signals goes low when margining and high when complete.

APPLICATIONS INFORMATION (CONTINUED)