ADA4625-1ARDZ-R7 datasheet(20/30 Pages) AD

20 / 30 page

ADA4625-1

Data Sheet

Rev. 0 | Page 20 of 30

THEORY OF OPERATION

Figure 67 shows the simplified circuit diagram for the

ADA4625-1. The JFET input stage architecture offers the

advantages of low input bias current, high bandwidth, high

gain, low noise, and no phase reversal when the applied input

signal exceeds the common-mode voltage range. The output

stage is rail to rail with high drive characteristics and low

dropout voltage for both sinking and sourcing currents.

INPUT AND GAIN STAGES

To achieve high input impedance, low noise, low offset, and low

offset drift, the ADA4625-1 uses large input N channel JFETs

(M1 and M2). These JFETs operate with the S source at about

1.2 V above the G gate. In the worst case, the source is only 0.9 V

above the gate. By design, the normal operation of the input tail

current (ITAIL) extends down to 0.6 V above V−, which gives the

ADA4625-1 an input common-mode range down to 0.2 V below

V− with margin. Resistive loads keep the noise low. The BUFF1

buffer drives the top of the input load resistors (R1 and R2),

keeping the voltage drop across M1 and M2 nearly constant,

making a virtual cascode. The differences of the input voltages

of +IN and –IN steer ITAIL through M1 and M2 to R1 and R2,

generating a differential voltage. The first voltage to current gain

block (GM1) translates that differential voltage into differential

currents (I1 and I2) that drive the current mirror (Q1 and Q2),

which generates a differential voltage between the reference

node and gain node. JFET inputs of the second voltage to

current gain block (GM2) maximizes the gain node impedance,

giving the ADA4625-1 a high gain.

OUTPUT STAGE

The GM2 gain block generates two pairs of differential currents.

One pair drives the bottom current mirror (Q3 and Q4) and the

NPN output transistor (Q7), and the second pair drives the top

current mirror (Q5 and Q6) and the output PNP transistor (Q8).

The common emitter output transistors (Q7 and Q8) source and

sink current rail to rail. GM2 also senses the base voltages of Q7

and Q8 and adjusts the I4 and I6 currents; with no output load,

Q7 and Q8 collector currents are 0.6 mA. In addition, GM2

clamps the base voltages of Q7 and Q8 so neither completely

turns off.

+IN

V–

V+

INPUT

TAIL CURRENT

–IN

OUT

TCVOS

TRIM

JFET

INPUT PAIR

5 V

LEVEL SHIFT

Q10

BIAS

ITC1

ITAIL

ITC2

CCOMP2

CCOMP1

OUTPUT

PNP

OUTPUT

NPN

–IN

GM1

DIFFERENTIAL

VOLTAGE

INPUT LOAD

RESISTORS

AND VOS TRIM

DIFFERENTIAL

CURRENTS

GAIN NODE

REF NODE

V/I GAIN

BUFF1

GM2

V/I GAIN AND

OUTPUT

BIAS

Figure 67. Simplified Circuit Diagram

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