LM12434CIWM datasheet(70/80 Pages) NSC

70 / 80 page

70 Digital Interface (Continued)

74 I2C BUS INTERFACE

The I2C bus is a serial synchronous bus structure It is a

multi-master bus which means that more than one device

capable of controlling the bus can be connected to it The

bus uses 2 wires serial data (SDA) and serial clock (SCL)

to carry information between the devices connected to the

bus Both data and clock lines are bidirectional and are con-

nected to the positive power supply via a pull-up resistor

Each device is identified by a unique address whether it is a

microprocessorcontroller or a peripheral such as memory

keyboard data-converter or display Each device can oper-

ate as either transmitter or receiver depending on the func-

tion of the device In addition to transmitters and receivers

devices can also be considered as masters and slaves

when performing data transfer A master is the device that

initiates a data transfer on the bus and generates the clock

signals to permit that transfer At that time any device ad-

dressed is considered slave It should be apparent that the

I2C bus is not merely an interconnecting wire it embodies

comprehensive formats and procedures for addressing

transfer cycles start and stop clock generationsynchroni-

zation and bus arbitration The following discussion as-

sumes that the reader is familiar with the specification and

architecture of the I2C bus

The LM12434 and LM12 L 438’s I2C bus interface is se-

lected when the MODESEL1 and MODESEL2 pins have the

logic state of ‘‘10’’

Figure 18 shows a typical connection

diagram for the LM12434 and LM12 L 438 to the I2C bus

As was mentioned communication on the I2C bus is per-

formed on 2 lines SCL (serial clock) and SDA (serial data)

pins P5 and P4 are assigned to these lines The DAS oper-

ates as a slave on the I2C bus As a result the SCL line is

an input (no clock is generated by the LM12434 and

LM12 L 438) and the SDA line is a bi-directional serial data

path According to I2C bus specifications the DAS has a

7-bit slave address The four most significant bits of the

slave address are hard wired inside the LM12434 and

LM12 L 438 and are ‘‘0101’’ The three least significant

bits of the address are assigned to pins P3 – P1 Therefore

the LM12434 and LM12 L 438 I2C slave address is

MSB

LSB

Tying the P3 – P1 pins to different logic levels allows up to

eight LM12434 and LM12 L 438’s to be addressed on a

single I2C bus

Figure 17 shows the timing diagram for the read and write

cycles for the LM12434 and LM12 L 438’s I2C interface

This timing diagram depicts the general relationship be-

tween the serial clock edges and the data bits It is not

meant to show guaranteed timing performance (See speci-

fication tables for parametric switching characteristics) The

DAS’s I2C interface timing parameters fully meet or exceed

the I2C bus specification Data transfer on the I2C bus is

byte oriented and the 16-bit data to be written to or read

from each register is transferred in two bytes

Write cycle

A write cycle is illustrated in

Figure 17a Com-

munication is initiated with a start condition generated by a

master (I2C bus specification) followed by a byte of the

DAS’s slave address with the readwrite bit (8th bit) being

‘‘0’’ indicating a write cycle will follow At the 9th SCL clock

pulse of the first data packet the DAS pulls the SDA line

low (‘‘0’’) to acknowledge that it has been addressed The

next byte is the address of the DAS register to be accessed

The format of this byte is three ‘‘0’s’’ (MSBs) followed by

four bits of register address (MSB first as shown) and a ‘‘0’’

as the last bit (LSB) After the DAS acknowledges the ad-

dress byte the 16-bit data proceeds in two bytes beginning

with the high order byte (MSB first) The direction of the

data in a write cycle is from master to DAS with acknowl-

edgement given by the DAS at the end of each byte The

cycle is completed by a stop condition generated by the

master

Readburst read cycle

The read and burst read cycles for

the I2C interface are combined in a single format A read

cycle is shown in

Figure 17b A read cycle starts the same

as a write with a slave address byte for write followed by a

ten to the DAS the bus should be released without any stop

condition The master then applies a repeat start condition

followed by the DAS’s slave address but with the read

write bit being ‘‘1’’ indicating a read request from the mas-

ter The DAS (slave) acknowledges its address and begin-

ning with the next byte the direction of the data will be from

DAS to master The DAS starts to transmit the contents of

its register (addressed previously at second byte of the cy-

cle) synchronized with the clocks applied by the master An

even number of data bytes should be read from the DAS

(two bytes per register) At the end of each byte received

from the DAS the bus master generates an acknowledge

The DAS continues to repeat transmitting its register con-

tents as long as the master is transmitting clocks and ac-

knowledges at the end of each byte The DAS recognizes

the end of the transfer whenever the master does not ac-

knowledge at the end of an even numbered byte At this

point the master should generate a stop condition as re-

quired by the I2C bus specification Notice that the master

may read only one word (single read) or as many words (two

bytes each) as it needs using the read procedure

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