AD6624ASSLASHPCB datasheet(28/40 Pages) AD

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AD6624A

–28–

Table VIII. Channel Address Memory Map (continued)

Ch Address

Bit Width

Comments

BIST Signature for I Path

BIST-I

BIST Signature for Q Path

BIST-Q

# of BIST Outputs to Accumulate

19–0: # of Outputs (Counter Value Read)

RAM BIST Control Register

D-RAM Fail/Pass

C-RAM Fail/Pass

RAM BIST Enable

Serial Port Control Register

Map RCF Data to BIST Registers

8–7:

I_SDFS Control

1x:

Separate I and Q SDFS Pulses

01:

SDFS High for Entire Frame

00:

Single SDFS Pulse

6–5:

SOWL

1x:

24-Bit Words

01:

16-Bit Words

00:

12-Bit Words

SBMx

3–0:

SDIVx[3:0]

Serial Output Frame Timing (Master and Slave)

The SDFS signal transitions accordingly depending on whether

the part is in Master (SBM = 1, Figure 43) or Slave (SBM = 0,

Figure 32) mode. The next rising edge of SCLK after this occurs

will drive the first bit of the serial data on the SDO pin. The

falling edge of SCLK or the subsequent rising edge can then be

used by the DSP to sample the data until the required number

of bits is received (determined by the serial output port word

length). If the DSP has the ability to count bits, the DSP will

know when the complete frame is received. If not, the DSP can

monitor the SDFE pin to determine that the frame is complete.

Serial Port Timing Specifications

Whether the AD6624A serial channel is operated as a Serial

Bus Master or as a Serial Slave, the serial port timing is iden-

tical. Figures 38 to 44 indicate the required timing for each of

the specifications.

SCLK

tSCLKL

tSCLK

tSCLKH

Figure 37. SCLK Timing Requirements

CLK

SCLK

tDSCLKH

tSCLKH

tSCLKL

Figure 38. SCLK Switching Characteristics (Divide by 1)

SCLK

SDI

DATA

tSSI

tHSI

Figure 39. Serial Input Data Timing Requirements

SCLK

SDO

I15

I14

tDSDO

I13

Figure 40. Serial Output Data Switching Characteristics

SCLK

SDFS

tSSF

tHSF

Figure 41. SDFS Timing Requirements (SBM = 0)

SDO

IMSB

SDFS

SCLK

tDSO

IMSB1

SDFS MINIMUM

WIDTH IS ONE SCLK

FIRST DATA IS AVAILABLE THE FIRST

RISING SCLK AFTER SDFS GOES HIGH

Figure 42. Timing for Serial Output Port (SBM = 1)

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