MPC755 datasheet(8/56 Pages) MOTOROLA

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 2 shows the allowable undershoot and overshoot voltage on the MPC755.

Figure 2. Overshoot/Undershoot Voltage

The MPC755 provides several I/O voltages to support both compatibility with existing systems and migration to

future systems. The MPC755 core voltage must always be provided at nominal 2.0 V (see Table 3 for actual

recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets

of supply pins and may be provided at the voltages shown in Table 2. The input voltage threshold for each bus is

selected by sampling the state of the voltage select pins BVSEL and L2VSEL during operation. These signals must

remain stable during part operation and cannot change. The output voltage will swing from GND to the maximum

voltage applied to the OVDD or L2OVDD power pins.

Table 2 describes the input threshold voltage setting.

Table 2. Input Threshold Voltage Setting

Part

Revision

BVSEL Signal

Processor Bus

Interface Voltage

L2VSEL Signal

L2 Bus

Interface Voltage

Not Available

2.5 V/3.3 V

Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied.

Note: The input threshold settings above are different for all revisions prior to Rev. 2.8 (Rev. E). For more information, refer to Section 10.2,

“Part Numbers Not Fully Addressed by This Document.”

VIH

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

(L2)OVDD + 20%

VIL

(L2)OVDD

(L2)OVDD + 5%

of tSYSCLK

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