AT89C51ED2-RDTIM datasheet(17/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Enhanced Features

In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new fea-

tures, which are:

•

X2 option

•

Dual Data Pointer

•

Extended RAM

•

Programmable Counter Array (PCA)

•

Hardware Watchdog

•

SPI interface

•

4-level interrupt priority system

•

Power-off flag

•

ONCE mode

•

ALE disabling

•

Some enhanced features are also located in the UART and the Timer 2

X2 Feature

The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature

called ‘X2’ provides the following advantages:

•

Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

•

Save power consumption while keeping same CPU power (oscillator power saving).

•

Save power consumption by dividing dynamically the operating frequency by 2 in

operating and idle modes.

•

Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by software.

Description

The clock for the whole circuit and peripherals is first divided by two before being used

by the CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.

Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge

of the XTAL1

÷ 2 to avoid glitches when switching from X2 to STD mode. Figure 6

shows the switching mode waveforms.

Figure 5. Clock Generation Diagram

XTAL1

CKCON0

8-bit Prescaler

FOSC

FXTAL

XTAL1:2

FCLK CPU

FCLK PERIPH

CKRL

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