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SSM2518CPZ-R7 Scheda tecnica(PDF) 37 Page - Analog Devices |
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SSM2518CPZ-R7 Scheda tecnica(HTML) 37 Page - Analog Devices |
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37 / 48 page ![]() Datasheet SSM2518 Rev. B | Page 37 of 48 DRC CONTROL 2 REGISTER Address: 0x0B, Reset: 0x5B, Name: DRC_Control_2 Table 24. Bit Descriptions for DRC_Control_2 Bits Bit Name Settings Description Reset Access [7:4] PEAK_ATT DRC Peak Detector Attack Time. 0x5 RW 0000 0 ms 0001 0.09 ms 0010 0.19 ms 0011 0.37 ms 0100 0.75 ms 0101 1.5 ms 0110 3 ms 0111 6 ms 1000 12 ms 1001 24 ms 1010 48 ms 1011 96 ms 1100 192 ms 1101 384 ms 1110 768 ms 1111 1.536 sec [3:0] PEAK_REL DRC Peak Detector Release Time. 0xB RW 0000 0 ms 0001 1.5 ms 0010 3 ms 0011 6 ms 0100 12 ms 0101 24 ms 0110 48 ms 0111 96 ms |
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