PEX 8732, PCI Express Gen 3 Switch, 32 Lanes, 12 Ports

© PLX Technology, www.plxtech.com

Page 4 of 5

10/20/2010, Version 1.0

Error Injection & SerDes Loopback

Using the PEX 8732’s Error Injection feature, users can

inject malformed packets and/or fatal errors into their

system and evaluate a system’s ability to detect and

recover from such errors. The PEX 8732 also supports

Internal Tx, External Tx, Recovered Clock, and Recovered

Data Loopback modes.

Applications

Suitable for host-centric as well as peer-to-peer traffic

patterns, the PEX 8732 can be configured for a wide

variety of form factors and applications.

Host Centric Fan-out

The PEX 8732, with its symmetric or asymmetric lane

configuration capability, allows user-specific tuning to a

variety of host-centric applications. Figure 6 shows a

server design where, in a quad or multi processor system,

users can assign endpoints/slots to CPU cores to distribute

the system load. The packets directed to different CPU

cores will go to different (user assigned) PEX 8732

upstream ports, allowing better queuing and load balancing

capability for

higher

performance.

Conversely, the

PEX 8732 can

also be used in

single-host mode

to simply fan-out

to endpoints.

Figure 6. Host Centric Dual Upstream

Multi-Host Systems

In multi-host mode, the PEX 8732 can be shared by up to

six hosts in a

system. By

creating six

virtual

switches, the

PEX 8732

allows six

hosts to fan-

out to their

respective

endpoints.

This reduces

the number of

Figure 7. Multi-Host System

switches required for fan-out, saving precious board space

and power consumption. In Figure 7, the PEX 8732 is

being shared by four different servers (hosts) with each

server is running its own applications (I/Os). The PEX

8732 assigns the endpoints to the appropriate host and

isolates them from the other hosts.

Host Failover

The PEX 8732 can also be utilized in applications where

host failover is required. In the below application (Figure

8), two hosts may be active simultaneously and controlling

their own domains while exchange status information

through doorbell registers or I

be programmed to trigger fail-over if the heartbeat

information is not p

In the event of a failure, the

surviving device will r

the endpoints connect

the failing CPU and

enumerate them in its own

domain without impactin

the operation of endpoints

already in its domain.

rovided.

eset

ed to

g

Figure 8. Host Fail-Over

+1 Fail-Over in Storage Systems

so be used to

a

er

N

The PEX 8732’s Multi-Host feature can al

develop storage array clusters where each host manages

set of storage devices independent of others (Figure 9).

Users can designate one of the hosts as the failover-host

for all the other hosts while actively managing its own

endpoints. The failover-host will communicate with oth

hosts for status/heartbeat information and execute a

failover event if/when it gets triggered.

x4

x4

x4

x4

x4

x4

x4

x4

CPU

CPU

PEX 8732

8 Disk Chassis

FC

x4

x4

FC

PEX 8712

CPU

CPU

CPU

CPU

CPU

CPU

8 Disk Chassis

FC

x4

x4

FC

PEX 8712

8 Disk Chassis

FC

x4

x4

FC

PEX 8716

8 Disk Chassis

FC

x4

x4

FC

PEX 8716

Figure 9. N+1 Failover

Memory

CPU

CPU

CPU

CPU

x8

x4s

x4s

x1s

SATA

Endpoint

PCIe Gen1, Gen2, or Gen3 slots

x8

PEX 8732

PCI

PCH

I/O

I/O

I/O

I/O

I/O

I/O

PEX 8732

I/O

I/O

Mem

CPU

CPU

CPU

CPU

PCH

I/Os

Mem

CPU

CPU

CPU

CPU

PCH

I/Os

Mem

CPU

CPU

CPU

CPU

PCH

I/Os

Mem

CPU

CPU

CPU

CPU

PCH

I/Os

CPU

CPU

CPU

CPU

x8

PEX 8732

CPU

CPU

CPU

CPU

x8

PEX 8732

x8s

x8s

x8s