© PLX Technology, www.plxtech.com

Page 1 of 5

10/7/2010, Version 1.0

PEX 8732, PCI Express Gen 3 Switch, 32 Lanes, 8 Ports

Figure 1. Common Port Configurations

PEX 8732

x4

PEX 8732

x8

PEX 8732

x8

PEX 8732

x16

3 x4

3 x8

10 x2

x8

8x2

x8

Highlights

Highlights

PEX 8732 General Features

PEX 8732 General Features

o

32-lane, 8-port PCIe Gen 3 switch

o

32-lane, 8-port PCIe Gen 3 switch

-

Integrate 8.0 GT/s SerDes

Integrate 8.0 GT/s SerDes

d

27 x 27mm

-

d

27 x 27mm

o

o

o

Typical Power: 6.0 Watts

o

Typical Power: 6.0 Watts

res

res

PEX 8732 Key Featu

o

a

PEX 8732 Key Featu

o

a

St ndards Compliant

-

PCI Express Base Specification, r3.0

)

St ndards Compliant

-

PCI Express Base Specification, r3.0

)

(compatible w/ PCIe r1.0a/1.1 & 2.0

ec, r1.2

(compatible w/ PCIe r1.0a/1.1 & 2.0

ec, r1.2

-

PCI Power Management Sp

-

PCI Power Management Sp

-

Microsoft Vista Compliant

ices

-

Microsoft Vista Compliant

ices

-

Supports Access Control Serv

-

Supports Access Control Serv

-

Dynamic link-width control

peed control

-

Dynamic link-width control

peed control

-

Dynamic SerDes s

o

gh

-

Dynamic SerDes s

o

gh

Hi

Performance

♦

Hi

Performance

♦

performancePAK

ng (bandwidth throttling)

performancePAK

ng (bandwidth throttling)

Read Paci

Read Paci

Multicast

t Pool

Multicast

t Pool

Dynamic Buffer/FC Credi

ic

Dynamic Buffer/FC Credi

ic

-

Non-blocking switch fabr

-

Non-blocking switch fabr

-

Full line rate on all ports

-

Packet Cut-Thru with 106ns max packet

-

Full line rate on all ports

-

Packet Cut-Thru with 106ns max packet

latency (x8 to x8)

latency (x8 to x8)

-

2KB Max Payload Size

o

-

2KB Max Payload Size

o

Flexible Configuration

6

Flexible Configuration

6

-

Ports configurable as x1, x2, x4, x8, x1

-

Registers configurable with strapping

2

t software

-

Ports configurable as x1, x2, x4, x8, x1

-

Registers configurable with strapping

2

t software

pins, EEPROM, I C, or hos

pins, EEPROM, I C, or hos

-

Lane and polarity reversal

-

Lane and polarity reversal

-

Compatible with PCIe 1.0a PM

o

-

Compatible with PCIe 1.0a PM

o

Multi-Host & Fail-Over Support

sparent (NT) port

Multi-Host & Fail-Over Support

sparent (NT) port

-

Configurable Non-Tran

-

Configurable Non-Tran

-

Failover with NT port

-

Up to 6 upstream/Host ports with 1+1 or

tream ports

-

Failover with NT port

-

Up to 6 upstream/Host ports with 1+1 or

tream ports

N+1 failover to other ups

o

N+1 failover to other ups

o

Quality of Service (QoS)

Quality of Service (QoS)

-

Eight traffic classes per port

-

Weighted round-robin source

-

Eight traffic classes per port

-

Weighted round-robin source

port arbitration

o

ailability, Serviceability

port arbitration

o

ailability, Serviceability

Reliability, Av

♦

Reliability, Av

♦ visionPAK

visionPAK

Per Port Performance Monitoring

header counters

Per Port Performance Monitoring

header counters

Per port payload &

Per port payload &

SerDes Eye Capture

SerDes Eye Capture

PCIe Packet Generator

PCIe Packet Generator

Error Injection and Loopback

nals

Error Injection and Loopback

nals

-

3 Hot Plug Ports with native HP Sig

-

All ports hot plug capable thru I

port)

-

3 Hot Plug Ports with native HP Sig

-

All ports hot plug capable thru I

port)

(Hot Plug Controller on every

bit support

(Hot Plug Controller on every

bit support

-

ECRC and Poison

-

ECRC and Poison

-

Data Path parity

-

Data Path parity

-

Memory (RAM) Error Correction

ignals

-

Memory (RAM) Error Correction

ignals

-

INTA# and FATAL_ERR# s

-

INTA# and FATAL_ERR# s

-

Advanced Error Reporting

-

ailable

-

Advanced Error Reporting

-

ailable

Port Status bits and GPIO av

Port Status bits and GPIO av

• Per port error diagnostics

• Per port error diagnostics

-

JTAG AC/DC boundary scan

-

JTAG AC/DC boundary scan

The ExpressLane™ PEX 8732 device offers Multi-Host PCI Express

switching capability enabling users to connect multiple hosts to their

respective endpoints via scalable, high bandwidth, non-blocking

interconnection to a wide variety of applications including servers,

storage, communications, and graphics platforms. The PEX 8732 is

well suited for fan-out, aggregation, and peer-to-peer traffic patterns.

The ExpressLane™ PEX 8732 device offers Multi-Host PCI Express

switching capability enabling users to connect multiple hosts to their

respective endpoints via scalable, high bandwidth, non-blocking

interconnection to a wide variety of applications including servers,

storage, communications, and graphics platforms. The PEX 8732 is

well suited for fan-out, aggregation, and peer-to-peer traffic patterns.

Multi-Host Architecture

Multi-Host Architecture

The PEX 8732 employs an enhanced version of PLX’s field tested PEX 8632

PCIe switch architecture, which allows users to configure the device in legacy

single-host mode or multi-host mode with up to six host ports capable of 1+1

(one active & one backup) or N+1 (N active & one backup) host failover. This

powerful architectural enhancement enables users to build PCIe based systems

to support high-availability, failover, redundant, or clustered systems.

The PEX 8732 employs an enhanced version of PLX’s field tested PEX 8632

PCIe switch architecture, which allows users to configure the device in legacy

single-host mode or multi-host mode with up to six host ports capable of 1+1

(one active & one backup) or N+1 (N active & one backup) host failover. This

powerful architectural enhancement enables users to build PCIe based systems

to support high-availability, failover, redundant, or clustered systems.

High Performance & Low Packet Latency

High Performance & Low Packet Latency

The PEX 8732 architecture supports packet cut-thru with a maximum

latency of 106ns (x8 to x8). This, combined with large packet memory,

flexible common buffer/FC credit pool and non-blocking internal switch

architecture, provides full line rate on all ports for performance-hungry

applications such as servers and switch fabrics. The low latency enables

applications to achieve high throughput and performance. In addition to low

latency, the device supports a packet payload size of up to 2048 bytes,

enabling the user to achieve even higher throughput.

The PEX 8732 architecture supports packet cut-thru with a maximum

latency of 106ns (x8 to x8). This, combined with large packet memory,

flexible common buffer/FC credit pool and non-blocking internal switch

architecture, provides full line rate on all ports for performance-hungry

applications such as servers and switch fabrics. The low latency enables

applications to achieve high throughput and performance. In addition to low

latency, the device supports a packet payload size of up to 2048 bytes,

enabling the user to achieve even higher throughput.

Data Integrity

Data Integrity

The PEX 8732 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction circuitry

throughout the internal data paths as packets pass through the switch.

The PEX 8732 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction circuitry

throughout the internal data paths as packets pass through the switch.

Flexible Configuration

Flexible Configuration

The PEX 8732’s 8 ports can be

configured to lane widths of x1, x2,

x4, x8, or x16. Flexible buffer

allocation, along with the device's

flexible

packet

flow

control,

maximizes

throughput

for

applications

where

more

traffic

flows in the downstream, rather than

upstream, direction. Any port can be

designated as the upstream port,

which can be changed dynamically.

Figure 1 shows some of the PEX

8732’s common port configurations

in legacy Single-Host mode

The PEX 8732’s 8 ports can be

configured to lane widths of x1, x2,

x4, x8, or x16. Flexible buffer

allocation, along with the device's

flexible

packet

flow

control,

maximizes

throughput

for

applications

where

more

traffic

flows in the downstream, rather than

upstream, direction. Any port can be

designated as the upstream port,

which can be changed dynamically.

Figure 1 shows some of the PEX

8732’s common port configurations

in legacy Single-Host mode

PEX 8732, PCI Express Gen 3 Switch, 32 Lanes, 8 Ports

© PLX Technology, www.plxtech.com

Page 1 of 5

10/7/2010, Version 1.0

Figure 1. Common Port Configurations

PEX 8732

x4

PEX 8732

x8

PEX 8732

x8

PEX 8732

x16

3 x4

3 x8

10 x2

x8

8x2

x8

.