WM8950 datasheet(33/52 Pages) WOLFSON

Il numero della parte	WM8950

Spiegazioni elettronici	ADC WITH MICROPHONE INPUT AND PROGRAMMABLE DIGITAL FILTERS

PDF	52 Pages

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Produttore elettronici	WOLFSON [Wolfson Microelectronics plc]

Homepage	http://www.wolfsonmicro.com

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Preliminary Technical Data

WM8950

PTD Rev 2.1 June 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Sets the chip to be master over FRAME

and BCLK

0=BCLK and FRAME clock are inputs

1=BCLK and FRAME clock are outputs

generated by the WM8950 (MASTER)

4:2

BCLKDIV

000

Configures the BCLK and FRAME output

frequency, for use when the chip is

master over BCLK.

000=divide by 1 (BCLK=MCLK)

001=divide by 2 (BCLK=MCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or

PLL clock output (under control of

CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

Clock

generation

control

CLKSEL

Controls the source of the clock for all

internal operation:

0=MCLK

1=PLL output

Table 25 Clock Control

COMPANDING

The WM8950 supports A-law and

µ-law companding. Companding can be enabled on the ADC

audio interface by writing the appropriate value to the ADC_COMP register bit.

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