AD5693R/AD5692R/AD5691R/AD5693

Data Sheet

Rev. D | Page 8 of 26

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

RESET

3

LDAC

4

GND

5

10

9

SDA

8

SCL

7

A0

6

AD5693R/

AD5691R

TOP VIEW

(Not to Scale)

Figure 5. AD5693R/AD5691R Pin Configuration, 10-Lead MSOP

Table 7. AD5693R/AD5691R Pin Function Descriptions, 10-Lead MSOP

Pin No.

Mnemonic

Description

1

Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.

2

Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple the supply to GND.

3

RESET

Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and external

pins are ignored. The input and DAC registers are loaded with zero code value and control register loaded with

circuit does not initialize the device correctly until this pin is released.

4

LDAC

Load DAC. Transfers the content of the input register to the DAC register. It can be operated in two modes,

asynchronously and synchronously, as shown in Figure 4. This pin can be tied permanently low, and the DAC

updates when new data is written to the input register.

5

GND

Ground Reference.

6

A0

Programmable Address for Multiple Package Decoding. The address pin can be updated on-the-fly.

7

SCL

Serial Clock Line.

8

SDA

Serial Data Input/Output.

9

Reference Input/Output. In the AD5693R/AD5691R, this is a reference output pin by default. It is recommended

to use a 10 nF decoupling capacitor for the internal reference.

10

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.