AD5693RARMZ datasheet(21/26 Pages) AD

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Data Sheet

AD5693R/AD5692R/AD5691R/AD5693

Rev. D | Page 21 of 26

Table 12. Command Table1

Command Byte

Data High Byte

Data Low Byte

Operation

DB7

DB6

DB5

DB4

[DB3:DB0]

[DB7:DB3]

[DB2:DB0]

[DB7:DB4]

DB3

DB2

DB1

DB0

XXXX

XXXXX

XXX

XXXX

NOP: do nothing.

XXXX

DB15:DB11

DB10:DB8

DB7:DB4

DB32

DB22

DB12, 3

DB02,3

Write input register.

XXXX

XXXXX

XXX

XXXX

Update DAC register (

LDAC

software).

XXXX

DB15:DB11

DB10:DB8

DB7:DB4

DB32

DB22

DB12,3

DB02,3

Write DAC and input

registers.

XXXX

DB15:DB11

000

0000

Write control register.

X is don’t care.

This bit is a don’t care for the AD5691R.

This bit is a don’t care for the AD5692R.

Write Input Register

The input register allows the preloading of a new value for the

DAC register. The transfer from the input register to the DAC

software using Command 2.

If new data is loaded into the DAC register, the DAC register

automatically overwrites the input register.

Update DAC Register

This command transfers the contents of the input register to the

DAC register and, consequently, the VOUT pin is updated. The

data contained in the serial write is ignored.

This operation is equivalent to a software LDAC.

Write DAC Register

This command updates the DAC output on completion of the

write operation. The input register is refreshed automatically

with the DAC register value.

Write Control Register

The control register is used to set the power-down and gain

functions. It is also used to enable/disable the internal reference

and perform a software reset. See Table 13 for the control

Table 13. Control Register Bits

D15

D14

D13

D12

D11

Reset

PD1

PD0

REF

Gain

Gain Bit

The gain bit selects the gain of the output amplifier. Table 14

shows how the output voltage range corresponds to the state of

the gain bit.

Table 14. Gain Bit

Gain

Output Voltage Range

0 V to VREF (default)

0 V to 2 × VREF

REF Bit

In the AD5693R/AD5692R/AD5691R only, the on-chip reference

is on at power-up by default. This reference can be turned on or

off by setting a software programmable bit, DB12, in the control

the mode of operation.

To reduce the power consumption, it is recommended to disable

the internal reference if the device is placed in power-down mode.

Table 15. Reference Bit

REF

Reference Function

Reference enabled (default)

Reference disabled

PD0 and PD1 Bits

The AD5693R/AD5692R/AD5691R/AD5693 contain two

separate modes of operation that are accessed by writing to the

control register.

In normal mode, the output buffer is directly connected to the

VOUT pin.

In power-down mode, the output buffer is internally disabled

and the VOUT pin output impedance can be selected to a well

known value, as shown in Table 16.

Table 16. Operation Modes

Operating Mode

PD1

PD0

Normal Mode

Power-Down Modes

1 kΩ Output Impedance

100 kΩ Output Impedance

Three-State Output Impedance

In power-down mode, the device disables the output buffer but

does not disable the internal reference. To achieve maximum

power savings, it is recommended to disable the internal reference.

Disabling both the internal reference and the output buffer

results in the supply current falling to 2 μA at 5 V.

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