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AD9858

Rev. A | Page 28 of 32

Phase Offset Control

A 14-bit phase offset (θ) may be added to the output of the

phase accumulator by means of the phase offset words stored in

the memory registers. This feature provides the user with three

different methods of phase control.

The first method is a static phase adjustment, where a fixed

phase offset is loaded into the appropriate phase-offset register

and left unchanged. The result is that the output signal is offset

by a constant angle relative to the nominal signal. This allows

the user to phase align the DDS output with an external signal,

if necessary.

The second method of phase control is where the user regularly

updates the appropriate phase-offset register via the I/O port.

By properly modifying the phase offset as a function of time,

the user can implement a phase modulated output signal. The

rate at which phase modulation can be performed is limited by

both the speed of the I/O port and the frequency of SYSCLK.

The third method of phase control involves the profile registers,

in which the user loads up to four different phase-offset values

into the appropriate profiles. The user can then select among

the four preloaded phase-offset values via the AD9858 profile

select pins. Thus, the phase changes are accomplished by driving

the hardware pins rather than writing to the I/O port, thereby

avoiding the speed limitation imposed by the I/O port.

However, this method is restricted to only four phase-offset

values (one phase-offset value per profile). Each profile has an

associated frequency and phase value. Changing the current

profile updates both parameters, so care must be taken to

ensure that no unwanted parameter changes take place.

Note that the phase-offset value is routed through a unit delay

(z–1) block. This is done to ensure that updates of the phase-

offset values exhibit the same amount of latency as updates of

the frequency tuning word. Otherwise, if the user decides to

update both frequency and phase-offset values, the phase-offset

change would propagate through the device before the tuning

word change. The presence of the unit delay in the phase-offset

path ensures that both frequency and phase-offset changes

exhibit similar latency.

Profile Selection

A profile consists of a specific group of memory registers (see

Table 6). In the AD9858 each profile contains a 32-bit frequency

tuning word and a 14-bit phase-offset word. Each profile is

selectable via two external profile select pins (PS0 and PS1) as

defined in Table 12. The specific mapping of registers to profiles

is detailed in the Register Bit Descriptions section. The user

should be aware that selection of a profile is internally

synchronized with DDS CLK using the SYNCLK timing. That

is, SYNCLK is used to synchronize the assertion of the profile

select pins (PS0, PS1). Therefore, the PS0 and PS1 pins must be

set up and held around the rising edge of SYNCLK. The PS0

and PS1 inputs are designed for zero hold time and 3.5 ns

setup time.

Table 12.

PS1

PS0

Profile

The profiles are available to the user to provide rapid changing

of device parameters via external hardware, which alleviates the

speed limitations imposed by the I/O port. For example, the

user might preprogram the four phase offset registers with

values that correspond to phase increments of 90°. By

controlling the PS0 and PS1 pins, the user can implement π/2

phase modulation. The data modulation rate would be much

higher than that possible by repeatedly reloading a single phase-

offset register via the I/O port.

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