SA25F020 Advanced Information
SAIFUN
21
Write Status Register (WRSR)
The WRSR instruction enables the user to
select one of four levels of protection. The
SA25F020 is divided into four array
segments. The top quarter, top half or all of
the memory segments can be protected
(for more details, refer to Table 9). The
data within a selected segment is therefore
read-only.
Table 9. Block Write Protect Bits
Status Register Bits
Level
BP1
BP0
Array Addresses
Protected
0
0
0
None
1/4
0
1
30000 - 3FFFF
1/2
1
0
20000 - 3FFFF
All
1
1
00000 - 3FFFF
The WRSR instruction (as shown in
Table 10) also allows the user to enable or
disable the WPb pin via the WPBEN bit.
Hardware write protection is enabled when
the WPb pin is low and the WPBEN bit is
1, and disabled when either the WP pin is
high or the WPBEN bit is 0. When the
device is hardware write protected, writes
to the status register are disabled.
NOTE:
When the WPBEN bit is hardware write
protected, it cannot be changed back
to 0 while the WPb pin is held low.
Table 10. WPBEN Operation
WPb WPBEN WEN
Protected
Blocks
Un-
protected
Blocks
Status
Register
X
0
0
Protected
Protected Protected
X
0
1
Protected
Writeable Writeable
Low
1
0
Protected
Protected Protected
Low
1
1
Protected
Writeable Protected
High
X
0
Protected
Protected Protected
High
X
1
Protected
Writeable Writeable
The WRSR instruction is enabled:
1. When the WPb pin is held high and
the device has been previously write
enabled via the WREN instruction.
2. When the WPb pin is held low, the
WPBEN bit is 0 and the device has
been previously write enabled via the
WREN instruction.
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