IC-MR3 datasheet(2/63 Pages) ICHAUS

2 / 63 page

iC-MR3 13-BIT S&H SIN/COS INTERPOLATOR

WITH 2.5 V / 5 V CONTROLLER INTERFACES

Rev C1, Page 2/63

DESCRIPTION

The iC-MR3 is a universal sine-to-digital converter

with signal conditioning and various interfaces for

configuration and data communication. The Micro-

controllers can be connected through a parallel I/O

interface with an 8-bit bus width (12.5 MHz) or using

a serial I/O interface (4-pin SPI, 10 MHz). The serial

I/O interface can function as a sensor interface either

using the BiSS C protocol (up to 10 MHz, bidirectional)

or SSI protocol (up to 4 MHz).

In the analog signal path the iC-MR3 has precision

input amplifiers with an adjustable gain for differen-

tial or referenced voltage signals of 10 mV peak to

1 V peak or for current signals of approx. 10 µA to

300 µA (input pins PSI, NSI, PCI, and NCI). A sepa-

rate measurement input (VREF) enables signals to

be referenced to the sensor’s reference voltage.

The following signal conditioning unit can compensate

for typical sine/cosine sensor signal errors, such as

offset, amplitude, and phase errors. The conditioned

signals are filtered and output through analog line

drivers with an amplitude of typically 250 mV (output

pins PSO, NSO, PCO, and NCO). A differential 1 Vpp

signal to 100 Ω is available for line transmission.

A control signal is gained from the conditioned signals

to stabilize the sine/cosine output signals. This can

adjust the transmitting LED of optical encoder sys-

tems using the integrated 50 mA driver stage (output

ACO). With magnetic sensors, this driver output sup-

plies the iC-MR3 measuring bridges or can be used

as feedback for the bridge supply voltage. By tracking

the sensor supply, sensor temperature and ageing

effects are compensated for, the input signals are sta-

bilized, and precise calibration of the input signals is

maintained. This makes a constant interpolation accu-

racy possible across the entire operating temperature

range.

At the same time, the sensor is monitored to see

whether it is functioning properly. The amplitude and

offset of the input signals at pins PSI, NSI, PCI, and

NCI are checked, enabling wire-breakage or short cir-

cuits to be detected. The control unit operating limits

are also monitored so that an alarm can be signaled

through the I/O interface and/or at error output NERR,

when the brightness of the LED falls below a config-

urable value. This could be caused by a build up of

dust or ageing of the optical system.

The sine-to-digital conversion is performed by a fast in-

terpolator with a sample-&-hold circuit which resolves

a sine cycle with 13 bits either continuously or on

request. In parallel and independent of the interpola-

tor, a configurable 37-bit cycle counter logs the sine

and cosine zero crossings. This cycle counter is pro-

grammable and can take its start value from the serial

absolute data interface (ADI); the corresponding inter-

face master operates either using the BiSS C or the

SSI protocol.

For position measurement applications, the iC-MR3

differentiates between multiturn and singleturn data

using a selectable intersection on the cycle counter.

The position can be corrected accordingly using the

multiturn and singleturn offset values.

An integrated 12-bit A/D converter digitizes linear mea-

surement voltages at pin ADC for the evaluation of

KTY temperature sensors, for example. Measurement

of the calibratable converter is observed by settable

threshold values so that a permissible operating tem-

perature range with a lower and upper temperature

threshold can be monitored.

After power-on, the iC-MR3 collects its CRC protected

configuration data from an external I2C-EEPROM or

waits for the configuration from one of the I/O inter-

faces. An undervoltage reset zeroes internal registers

and is shown as a reset pulse at pin NRES, which

also serves as a reset input (low active).

Errors can always be masked and allocated to an

error bit (and displayed at the error message output

NERR) or a warning bit. The internal status registers

are available to the I/O interfaces which have a num-

ber of different commands (software reset, memory

verification, and error simulation).

The device offered here is a multi-functional iC that contains in-

tegrated BiSS C interface components. The BiSS C process is

protected by patent DE 10310622 B4 owned by iC-Haus GmbH.

Users benefit from the open BiSS C protocol with a free license

which is necessary when using the BiSS C protocol in conjunction

with this iC.

Download the license at

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