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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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COP8-NSDEV Scheda tecnica(PDF) 72 Page - National Semiconductor (TI) |
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COP8-NSDEV Scheda tecnica(HTML) 72 Page - National Semiconductor (TI) |
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72 / 83 page  22.0 Instruction Set (Continued) 22.4.9 No-Operation Instruction The no-operation instruction does nothing, except to occupy space in the program memory and time in execution. No-Operation (NOP) Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt service routine. 22.5 REGISTER AND SYMBOL DEFINITION The following abbreviations represent the nomenclature used in the instruction description and the COP8 cross- assembler. Registers A 8-Bit Accumulator Register B 8-Bit Address Register X 8-Bit Address Register S 8-Bit Segment Register SP 8-Bit Stack Pointer Register PC 15-Bit Program Counter Register PU Upper 7 Bits of PC Registers PL Lower 8 Bits of PC C 1 Bit of PSW Register for Carry HC 1 Bit of PSW Register for Half Carry GIE 1 Bit of PSW Register for Global Interrupt Enable VU Interrupt Vector Upper Byte VL Interrupt Vector Lower Byte Symbols [B] Memory Indirectly Addressed by B Register [X] Memory Indirectly Addressed by X Register MD Direct Addressed Memory Mem Direct Addressed Memory or [B] Meml Direct Addressed Memory or [B] or Immediate Data Imm 8-Bit Immediate Data Reg Register Memory: Addresses F0 to FF (Includes B, X and SP) Bit Bit Number (0 to 7) ← Loaded with ↔ Exchanged with www.national.com 72 |
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