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COP8-NSDEV Scheda tecnica(PDF) 74 Page - National Semiconductor (TI) |
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COP8-NSDEV Scheda tecnica(HTML) 74 Page - National Semiconductor (TI) |
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74 / 83 page ![]() 22.0 Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long [SP] ←PL, [SP−1]←PU,SP−2, PC←ii JSR Addr. Jump SubRoutine [SP] ←PL, [SP−1]←PU,SP−2, PC9…0←i JSRB Addr Jump SubRoutine Boot ROM [SP] ←PL, [SP−1]←PU,SP−2, PL ←Addr,PU←00, switch to flash JID Jump InDirect PL ←ROM (PU,A) RET RETurn from subroutine SP + 2, PL ←[SP], PU←[SP−1] RETSK RETurn and SKip SP + 2, PL ←[SP],PU←[SP−1], skip next instruction RETI RETurn from Interrupt SP + 2, PL ←[SP],PU←[SP−1],GIE←1 INTR Generate an Interrupt [SP] ←PL, [SP−1]←PU, SP−2, PC←0FF NOP No OPeration PC ←PC+1 22.7 INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. See the BYTES and CYCLES per INSTRUCTION table for details. Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. Arithmetic and Logic Instructions [B] Direct Immed. ADD 1/1 3/4 2/2 ADC 1/1 3/4 2/2 SUBC 1/1 3/4 2/2 AND 1/1 3/4 2/2 OR 1/1 3/4 2/2 XOR 1/1 3/4 2/2 IFEQ 1/1 3/4 2/2 IFGT 1/1 3/4 2/2 IFBNE 1/1 DRSZ 1/3 SBIT 1/1 3/4 RBIT 1/1 3/4 IFBIT 1/1 3/4 RPND 1/1 Instructions Using A & C CLRA 1/1 INCA 1/1 DECA 1/1 LAID 1/3 DCORA 1/1 RRCA 1/1 RLCA 1/1 SWAPA 1/1 SC 1/1 RC 1/1 IFC 1/1 IFNC 1/1 PUSHA 1/3 POPA 1/3 ANDSZ 2/2 Transfer of Control Instructions JMPL 3/4 JMP 2/3 JP 1/3 JSRL 3/5 JSR 2/5 JSRB 2/5 JID 1/3 VIS 1/5 RET 1/5 RETSK 1/5 RETI 1/5 INTR 1/7 NOP 1/1 www.national.com 74 |
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