54HC595 datasheet(7/9 Pages) SS

Il numero della parte	54HC595

Spiegazioni elettronici	8-bit shif t registers with 3-state output latches in bare die form

PDF	9 Pages

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Produttore elettronici	SS [Silicon Supplies]

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Figure 2 – Reset Propagation Delay & Timing

High Speed CMOS Logic – 54HC595

Rev 1.0

05/02/19

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

UNITS

2.0V

3.0V

4.5V

Minimum Hold Time,

SRCLK

to SER

(Figure 5)

6.0V

Input

tr = tf = 6ns

2.0V

3.0V

4.5V

Minimum

Recovery Time,

SRCLR

to SRCLK

(Figure 2)

trec

6.0V

Input

tr = tf = 6ns

2.0V

3.0V

4.5V

Minimum

Pulse Width,

SRCLR

(Figure 2)

6.0V

Input

tr = tf = 6ns

2.0V

3.0V

4.5V

Minimum

Pulse Width,

SRCLK

(Figure 1)

6.0V

Input

tr = tf = 6ns

2.0V

3.0V

4.5V

Minimum

Pulse Width,

RCLK

(Figure 6)

6.0V

Input

tr = tf = 6ns

2.0V

1000

3.0V

800

4.5V

500

Maximum Input Rise

and Fall Times,

(Figure 1)

tr, tf

6.0V

Input

tr = tf = 6ns

400

Timing Requirements6

Switching Waveforms

Figure 1 – Clock Propagation Delay & Output Timing

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