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54HC595 Scheda tecnica(PDF) 3 Page - Silicon Supplies

Il numero della parte 54HC595
Spiegazioni elettronici  8-bit shif t registers with 3-state output latches in bare die form
PDF  9 Pages
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Produttore elettronici  SS [Silicon Supplies]
Homepage  https://siliconsupplies.com/
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54HC595 Scheda tecnica(HTML) 3 Page - Silicon Supplies

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PARAMETER
SYMBOL
MIN
MAX
UNITS
DC Supply Voltage
VCC
2
6
V
DC Input or Output Voltage
VIN ,VOUT
0
VCC
V
Operating Temperature Range
TJ
-55
+125
°C
VCC = 2.0V
0
1000
ns
VCC = 4.5V
0
500
ns
Input Rise or Fall Times
VCC = 6.0V
tr, tf
0
400
ns
Recommended Operating Conditions4 (Voltages referenced to GND)
Absolute Maximum Ratings2
PARAMETER
SYMBOL
VALUE
UNIT
DC Supply Voltage (Referenced to GND)
VCC
-0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
VIN
-0.5 to VCC +0.5
V
DC Output Voltage
VOUT
-0.5 to VCC +0.5
V
DC Input Current, per pad
IIN
±20
mA
DC Output Current, per pad
IOUT
±35
mA
DC VCC or GND Current
ICC
±75
mA
Power Dissipation in Still Air
3
PD
750
mW
Storage Temperature Range
TSTG
-65 to 150
°C
High Speed CMOS Logic – 54HC595
Rev 1.0
05/02/19
2. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may
reduce device reliability. 3. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method.
Function Table1
4. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken
to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be
constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
INPUTS
OUTPUTS
SRCLK
RCLK
OE
SRCLR
SER
QH’
QN
FUNCTION
X
X
L
L
X
L
NC
LOW level on SRCLR only affects the shift registers
X
↑
L
L
X
L
L
Empty shift-register loaded into storage register
X
X
H
L
X
L
Z
Shift-register clear. Parallel outputs in high- impedance OFF-
state
↑
X
L
H
H
QG’
NC
Logic high level shifted into shift register stage 0. Content of
all shift register stages shifted through, e.g. previous state of
stage 6 (internal Q6’) appears on serial output(QH’)
X
↑
L
H
X
NC
Qn’
Contents of shift register stages (internal Qn’) transfers to the
storage register and parallel output stages
↑
↑
L
H
X
QG’
Qn’
Shift register contents shifted through. Previous shift register
content transfers to storage register & parallel output stages.
1. H=HIGH voltage level; L=LOW voltage level; ↑ =LOW-to-HIGH transition; Z=high-impedance OFF-state; NC=no change; X=don’t care.



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