NT5CC128M8GP-EKB datasheet(73/160 Pages) NANYA

73 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

ODT during Reads:

As the DDR3(L) SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle

before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble

as shown in the following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM

stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e. tHZ is late), then DRAM

complies with tAONmax timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read

than shown in this example.

ODT must be disabled externally during Reads by driving ODT low. (Example: CL=6;

AL=CL-1=5; RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8; ODTLoff=CWL+AL-2=8)

T11

T10

T12

T13

T14

T15

T16

CMD

Address

RL = AL + CL

RTT_NOM

RTT

ODTLoff = CWL + AL - 2

tAOFmax

tAOFmin

ODTLon = CWL + AL - 2

RTT_NOM

tAONmax

ODT

DRAM

ODT

DQSdiff

Din

b+1

Din

b+2

Din

b+3

Din

b+4

Din

b+5

Din

b+6

Din

b+7

Read

NOP

Valid

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