GD9FS1G8F2AMG datasheet(14/55 Pages) GIGADEVICE

Il numero della parte	GD9FS1G8F2AMG

Spiegazioni elettronici	Single level cell technology

PDF	55 Pages

Scroll/Zoom	100%

Produttore elettronici	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

Homepage	http://www.gigadevice.com/

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14 / 55 page

GD9Fx1GxF2A

7. BUS OPERATION

There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data

Output, Write Protect, and Standby. Typically glitches less than 5ns on Chip Enable, Write Enable and Read Enable are

ignored by the memory and do not affect bus operations.

CLE

ALE

CE#

WE#

RE#

WP#

MODE

Rising

Command input for read mode

Rising

Address input (4 cycles) for read mode

Rising

Command input for write mode

Rising

Address input (4 cycles) for write cycle

Rising

Data input

Falling

Sequential read and data output

During read(busy)

During program/Erase(busy)

Write protect

0V / VCC

Standby

Notes:

1. X can be VIL or VIH. H = Logic level HIGH. L = Logic level LOW.

2. WP# should be biased to CMOS high or CMOS low for stand-by mode.

3. WE# and RE# during Read Busy must be keep on high to prevent unplanned command/address/data input or to avert

unintended data out. In this time, only Reset and Read Status can be input to the device.

GD9FS1G8F2AMG Scheda tecnica(PDF) 14 Page - GigaDevice Semiconductor (Beijing) Inc.