UPD17P133CS datasheet(63/289 Pages) NEC

63 / 289 page

CHAPTER 7

SYSTEM REGISTER (SYSREG)

Figure 7-7. Index Register and Memory Pointer Configuration

Figure 7-8. Data Memory Address Modification by Index Register and Memory Pointer

BANK

Bank register

Memory pointer

Index register

MPE

Memory pointer enable flag

IXE

Index enable flag

MPH

Memory pointer's upper 3 bits

IXH

Index register's bits 10-8

MPL

Memory pointer's lower 4 bits

IXM

Index register's bits 7-4

General register column address

IXL

Index register's bits 3-0

General register pointer

Data memory address indicated by mR, mC

(

×)

Contents addressed with

Data memory row address

× : Direct address such as r

Data memory column address

7AH

Address

Name

Bit

Symbol

name

Data

Reset-time value

b3 b2 b1

b2 b1 b1

Index register (IX)

Memory pointer (MP)

IXH

MPH

IXM

MPL

IXL

0000

00000000000

(IX)

(MP)

Flag name

7BH

7CH

7FH

PSW

Program status

word

(PSWORD)'S

lower 4 bits

Data Memory Address Specified with m

IXE

Bank

BANK

IXH

Row address Column address

Bank

Row address Column address

Indirect Transfer Address Specified with @m

BANK

(r)

MPH

MPL

(r)

BANK

(r)

IXM

IXL

IXH

IXM

MPE

Setting disabled

Logical OR

Same as

above

UPD17P133CS Scheda tecnica(PDF) 63 Page - NEC

UPD17P133CS Scheda tecnica(HTML) 63 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL