ADA4625-1ARDZ-R7 datasheet(26/35 Pages) AD

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ADA4625-1/ADA4625-2

Data Sheet

Rev. A | Page 26 of 35

ADA4625-1 ADVANTAGES AND DESIGN EXAMPLE

The op amp choice for an active filter affects the key performance

parameters of the PLLs: frequency range, phase noise, spurious

frequencies, and lock time. The output of the filter directly

affects the generated frequency and phase. Low noise is

essential because any voltage noise applied to the tuning port

of the VCO is amplified by the VCO gain and translated into

phase noise. Low input bias current is also recommended

because the op amp bias current must be sourced from the PLL

phase detector/ charge pump, and any mismatch or leakage at

the output of the phase detector between the up and down

currents causes ripples and reference spurs.

With 18 MHz gain bandwidth product (GBP), low input bias

currents (±15 pA), low voltage noise density (3.3 nV/√Hz),

ultralow current noise density, and low 1/f corner frequency,

the ADA4625-1 is an ideal op amp for using in a PLL active

loop filter. The ADA4625-1 does not require a negative voltage

supply because of its ground sensing input. The rail-to-rail

output stage is beneficial in terms of increasing the flexibility

in biasing the op amp so that the output range of the PLL is

mapped efficiently onto the input range of the VCO. In

addition, the wide 5 V to 36 V operating supply range makes

the ADA4625-1 a versatile choice for the design of a wide

variety of active loop filters.

Figure 96 shows the ADA4625-1 as the loop filter for the

ADF4159, a 13 GHz fractional-N synthesizer. The phase

detector polarity of the ADF4159 is programmed to negative

because the ADA4625-1 is used in an inverting active loop filter

configuration. The VCO is set up to feedback the VCO/2 output

to the ADF4159. The loop filter has a 900 kHz loop bandwidth

(LBW) and a phase margin of 58° with 2.5 mA charge pump

current. Lowering the bandwidth further improves phase noise

at the expense of increased PLL lock time.

Figure 95 shows the PLL loop filter transfer function. Capacitor C1

and Resistor R1 change the phase detector current pulses into a

continuous time voltage waveform. At frequencies lower than

the R2C2 zero, the amplifier and R1C2 form an integrator.

Between the R2C2 zero and the R2C3 pole, the gain is constant

at the value set by R2/R1. Above the R2C3 pole, the amplifier is

an integrator until R1C3 becomes a feedforward noninverting

zero path around the amplifier. Resistor R3 and Capacitor C4

add an additional pole in the loop filter signal path. Setting the

R3C4 pole below the R2C3 pole reduces the effect of the R1C3

feedforward zero.

LOG FREQUENCY

0dB

R2C2 ZERO

R2/R1

AMP GAIN

R3C4 POLE

R2C3 POLE

R1C1 POLE

Figure 95. PLL Loop Filter Transfer Function

ADF4159

FRACTIONAL-N

SYNTHESIZER

11.4GHz TO 12.8GHz

VCO

RFINx

3.3V

1.8V

AVDD

VCC

DVDD

3.3V

AGND

GND

RFOUT

11.4GHz TO 12.8GHz

ADA4625-1

1µF

47kΩ

15V

3.3nF

33pF

1kΩ

100pF

52pF

VTUNE

RFOUT/2

5.7GHz TO 6.4GHz

3.3V

6dB PAD

6GHz

12GHz OUTPUT

REFIN

100MHz

DGND

SDGND

CPGND

220pF

100pF

100Ω

365Ω

Figure 96. Block Diagram of ADA4625-1 Active Loop Filter for ADF4159

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