ADRF5730BCCZN-R7 datasheet(16/19 Pages) AD

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ADRF5730

Data Sheet

Rev. 0 | Page 16 of 19

APPLICATIONS INFORMATION

EVALUATION BOARD

The ADRF5730-EVALZ is a 4-layer evaluation board. The top

and bottom copper layer are 0.5 oz (0.7 mil) plated to 1.5 oz

(2.2 mil) and are separated by dielectric materials. The stackup

for this evaluation board is shown in Figure 37.

Figure 37. Evaluation Board Stackup

All RF and dc traces are routed on the top copper layer, whereas

the inner and bottom layers are grounded planes that provide a

solid ground for the RF transmission lines. The top dielectric

material is 12 mil Rogers RO4003, offering optimal high

frequency performance. The middle and bottom dielectric

materials provide mechanical strength. The overall board

thickness is 62 mil, which allows 2.4 mm RF launchers to be

connected at the board edges.

Figure 38. Evaluation Board, Top View

The RF transmission lines are designed using a coplanar

waveguide (CPWG) model, with a trace width of 16 mil and

ground clearance of 6 mil to have a characteristic impedance of

50 Ω. For optimal RF and thermal grounding, as many through

vias as possible are arranged around transmission lines and

under the exposed pad of the package.

The ADRF5730-EVALZ does not have high frequency

impedance matching implemented on the RF transmission

lines. For more details on the impedance matched circuit, refer

to the Impedance Matching portion of the Probe Matrix Board

section.

Thru calibration can be used to calibrate out the board loss effects

from the ADRF5730-EVALZ evaluation board measurements to

determine the device performance at the pins of the IC. Figure 39

shows the typical board loss for the ADRF5730-EVALZ evaluation

board at room temperature, the embedded insertion loss, and the

de-embedded insertion loss for the ADRF5730.

Figure 39. Insertion Loss vs. Frequency

Figure 38 shows the actual ADRF5730 evaluation board with

component placement.

Two power supply ports are connected to the VDD and VSS test

points, TP1 and TP2, and the ground reference is connected to

the GND test point, TP4. On the supply traces, VDD and VSS, a

100 pF bypass capacitor is used to filter high frequency noise.

Additionally, unpopulated components positions are available

for applying extra bypass capacitors.

All the digital control pins are connected through digital signal

traces to the 2 × 9-pin header, P1. There are provisions for a

resistor capacitor (RC) filter that helps eliminate dc-coupled

noise. The ADRF5730 was evaluated without an external RC

filter, the series resistors are 0 Ω, and shunt capacitors are

unpopulated on the evaluation board.

The RF input and output ports (ATTIN and ATTOUT) are

connected through 50 Ω transmission lines to the 2.4 mm RF

launchers, J1 and J2, respectively. These high frequency RF

launchers are connected by contact and are not soldered onto

the board.

A thru calibration line connects the unpopulated J3 and J4

launchers. This transmission line is used to estimate the loss of

the PCB over the environmental conditions being evaluated.

The schematic of the ADRF5730-EVALZ evaluation board is

shown in Figure 40.

RO4003

1.5oz Cu (2.2mil)

0.5oz Cu (0.7mil)

1.5oz Cu (2.2mil)

W = 16mil

G = 6mil

T = 2.2mil

H = 12mil

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

FREQUENCY (GHz)

THRU LOSS

EMBEDDED INSERTION LOSS

DE-EMBEDDED INSERTION LOSS

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