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AM6548 Scheda tecnica(PDF) 7 Page - Texas Instruments |
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AM6548 Scheda tecnica(HTML) 7 Page - Texas Instruments |
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7 / 277 page  7 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Revision History Copyright © 2017–2019, Texas Instruments Incorporated 2 Revision History Changes from June 22, 2019 to December 20, 2019 (from H Revision (June 2019) to I Revision) Page • GLOBAL: Changed module name from MMC/SD to MMCSD ................................................................. 1 • Added links to Section 1.2, Applications ........................................................................................... 3 • Added in-line description linking to Section 1.3, Description .................................................................... 4 • Added links to header names in Table 3-1, Device Comparison ............................................................... 8 • Updated DDR_FS_RESETn signal description ................................................................................. 62 • Updated MMC/SD signals footnotes in Section 4.3.17, MMCSD ............................................................. 82 • Added active low description to MMC0/1_SDCD signal ....................................................................... 82 • Updated TEMP_DIODE_P signal description in Table 4-71, Miscellaneous0 Signal Descriptions ..................... 102 • Updated the names SOC_PADCONFIG_* and WKUP_PADCONFIG_* to CTRLMMR_PADCONFIG and CTRLMMR_WKUP_PADCONFIG* to match the TRM. ...................................................................... 106 • Added SerDes signals to Table 4-76, Unused Balls Specific Connection Requirements ................................ 117 • Updated Section 5.1, Absolute Maximum Ratings ........................................................................... 119 • Updated VDDSHV6 and VDDSHV7 to support only 1.8 V ................................................................... 119 • Removed Latch-up Performance parameter from Section 5.1, Absolute Maximum Ratings ............................ 119 • Updated Section 5.2, ESD Ratings .............................................................................................. 121 • Updated Section 5.4, Recommended Operating Conditions and Section 5.5, Operating Performance Points ....... 122 • Updated USB0_VBUS and USB1_VBUS parameters in Section 5.4, Recommended Operating Conditions ......... 124 • Added VILSS and VIHSS parameters to Section 5.6, Electrical Characteristics ............................................. 127 • Updated DNL and SMPL_CLK parameter in Table 5-8, Analog ADC DC Electrical Characteristics ................... 128 • Updated TCK electrical parameter for VIL in Table 5-11, LVCMOS Buffers DC Electrical Characteristics ............ 131 • Updated VIH parameter for 3.3-V mode in Table 5-13, LVCMOS-FS Buffers DC Electrical Characteristics .......... 133 • Updated electrical characteristic parameters in Table 5-28, WKUP_LFOSC0 Crystal Electrical Characteristics ..... 155 • Added new Section 5.9.4.1.7, WKUP_LFOSC0 LVCMOS Digital Clock Source .......................................... 156 • Removed Interface Clock Specifications section and added Section 5.9.4.5, Module and Peripheral Clock Frequencies ........................................................................................................................ 159 • Updated timing specification values in Section 5.9.5.2, CPSW2G .......................................................... 160 • Updated timing specification values in Section 5.9.5.10, GPMC and Section 5.9.5.14, MCASP ....................... 171 • Updated McSPI setup and delay timing values for master and slave mode ............................................... 201 • Updated timing specification values in Section 5.9.5.16, eMMC/SD/SDIO ................................................ 207 • Updated Table 5-77, Switching Characteristics for MMCi - SDR104 / HS200 Mode ..................................... 212 • Updated Table 5-83, OSPI Switching Characteristics - Data Training ...................................................... 217 • Updated timing parameters in Section 5.9.5.19, OLDI ....................................................................... 221 • Updated timing specification values in Section 5.9.5.21, PRU_ICSSG .................................................... 224 • Removed duplicate details in Section 6, Detailed Description that also appears in device TRM ....................... 240 • Updated all subsections in Section 7, Applications, Implementation, and Layout to rearrange in general sections . 253 • Added Section 7.2.7, Integrated Power Management Features ............................................................. 258 • Added note about high-frequency decoupling capacitor in Figure 7-6, External Decoupling Capacitor Connections 258 • Updated VDDSHV6 and VDDSHV7 to support only 1.8 V ................................................................... 260 |
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