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AM6548 Scheda tecnica(PDF) 82 Page - Texas Instruments |
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AM6548 Scheda tecnica(HTML) 82 Page - Texas Instruments |
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82 / 277 page  82 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Terminal Configuration and Functions Copyright © 2017–2019, Texas Instruments Incorporated Table 4-44. MCSPI0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_SPI0_CS3 SPI Chip Select 3 IO AC3 MCU_SPI0_D0 SPI Data 0 IO Y3 MCU_SPI0_D1 SPI Data 1 IO Y2 Table 4-45. MCSPI1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_SPI1_CLK SPI Clock IO AF4 MCU_SPI1_CS0 SPI Chip Select 0 IO AD1 MCU_SPI1_CS1 SPI Chip Select 1 IO P4 MCU_SPI1_CS2 SPI Chip Select 2 IO P5 MCU_SPI1_CS3 SPI Chip Select 3 IO AD3 MCU_SPI1_D0 SPI Data 0 IO AF3 MCU_SPI1_D1 SPI Data 1 IO AE3 4.3.17 MMCSD 4.3.17.1 MAIN Domain Table 4-46. MMCSD0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC0_CALPAD(1) MMC/SD Calibration Resistor A D24 MMC0_CLK(2)(3)(4) MMC/SD Clock O B25 MMC0_CMD(2)(4) MMC/SD Command IO B27 MMC0_DS MMC Data Strobe I C25 MMC0_SDCD SD Card Detect (active low) I A23 MMC0_SDWP SD Write Protect I B23 MMC0_DAT0(2)(4) MMC/SD Data IO A26 MMC0_DAT1(2)(4) MMC/SD Data IO E25 MMC0_DAT2(2)(4) MMC/SD Data IO C26 MMC0_DAT3(2)(4) MMC/SD Data IO A25 MMC0_DAT4(2)(4) MMC/SD Data IO E24 MMC0_DAT5(2)(4) MMC/SD Data IO A24 MMC0_DAT6(2)(4) MMC/SD Data IO B26 MMC0_DAT7(2)(4) MMC/SD Data IO D25 (1) An external 10kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) When MMCSD0 or MMCSD1 is used, any non-MMC signal function multiplexed with the respective pins are not available. This is due to the MMC having an internal IO multiplexer which is controlled by MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE. This internal IO multiplexer is primary for the signal functions associated with MMCSD pins, and the PADCONFIG’s MUXMODE is secondary. Additionally, the internal IO multiplexer affects all of the MMCSD0 or MMCSD1 pins, regardless of configured data bus width. Therefore, when MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE = 0, the respective MMCSD pins are configured for eMMC/SD functionality, regardless of the PADCONFIG [MUXMODE] setting. (3) This output signal is also used as a retiming input. It is also recommended to place a 33 Ω resistor in series (close to the processor) to avoid signal reflections. (4) Each of these signals should have an external 50kΩ pull-up resistor connected to the corresponding power supply. |
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