MA2901

6

PIN DESCRIPTION

Figure 8: Pin Description

Name

I/O

Description

I

The four address inputs to the register stack used to select one register whose

contents are displayed through the A port

I

The four address inputs to the register stack used to select one register whose

contents are displayed through the B port and into which new data can be written

when the clock goes LOW

I

The nine instruction control lines. Used to determine what data sources will be

I/O

Electrically these lines are three-state outputs connected to TTL inputs internal to

the three state outputs are enabled and the MSB of the Q-register is available on

Otherwise, the three state outputs are electrically OFF (high impedance) and the

pins are electrically LS-TTL inputs. When the destination code calls for a down

shift, the pins are used as the data inputs to the MSB of the Q-register (Octal 4)

and RAM (Octal 4 or 5)

I/O

between devices for up and down shifts of the Q-register and ALU data.

I

Direct data inputs. A four-bit data field which may be selected as one of the ALU

O

The four data outputs. These are three-state output lines. When they are enabled,

they display either the four outputs of the ALU or the data on the A-port of the

OEN

I

Output enable. When OEN is HIGH, the Y outputs are OFF; when OEN is LOW, the

Y outputs are active (HIGH or LOW)

GN,PN

O

The carry generate and propagate outputs of the internal ALU. These signals are

used with the MA2901 for carry lookahead.

OVR

O

Overflow. This pin is logically the Exclusive OR of the carry-in and carry-out of the

MSB of the ALU. At the most significant end of the word, this pin indicates that the

result of an arithmetic two’s complement operation has overflowed into the sign-bit

F = 0

O

This is an open collector output which goes HIGH(OFF) if the data on the four ALU

operation is zero

O

The most significant ALU output bit.

I

The carry-in to the internal ALU.

O

The carry-out of the ALU internal ALU.

CP

I

The clock input. The Q-register and register stack outputs change on the clock

LOW - to HIGH transition. The clock LOW time is internally the write enable to the

16 x 4 RAM which compromises the “master” latches of the register stack. While

the clock is LOW, the “slave” latches on the RAM outputs are closed, storing the

data previously on the RAM outputs. This allows synchronous master-slave

operation of the register stack.