44

Read Cycle Dynamic Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

LIMITS

UNITS

(V)

MIN

MAX

MIN

MAX

Access Time From Address Change

5

-

610

-

825

ns

10

-

320

-

375

ns

Access Time From Chip Select

5

-

610

-

825

ns

10

-

320

-

375

ns

Output Active From MRD

5

-

610

-

825

ns

10

-

320

-

375

ns

NOTE:

1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.

FIGURE 1. READ CYCLE TIMING DIAGRAM

(NOTE 1)

(NOTE 1)

HIGH IMPEDANCE

MRD

MA

CS

DATA OUT

CDP1824/3, CDP1824C/3