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CDP1824CD3 Scheda tecnica(PDF) 4 Page - Intersil Corporation

Il numero della parte CDP1824CD3
Spiegazioni elettronici  High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory
PDF  5 Pages
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1824CD3 Scheda tecnica(HTML) 4 Page - Intersil Corporation

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All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Write Cycle Dynamic Electrical Specifications
Input tR, tF ≤ 15ns, CL = 50pF
PARAMETER
SYMBOL
TEST
CONDITIONS
LIMITS
UNITS
-55oC, +25oC+125oC
VDD
(V)
(NOTE 1)
MIN
MAX
(NOTE 1)
MIN
MAX
Write Pulse Width
tWRW
5
350
-
475
-
ns
10
180
-
220
-
ns
Data Setup Time
tDS
5
400
-
560
-
ns
10
190
-
260
-
ns
Data Hold Time
tDH
570
-
90
-
ns
10
35
-
45
-
ns
Chip Select Setup Time
tCS
5
550
-
775
-
ns
10
340
-
475
-
ns
Address Setup Time
tAS
5
550
-
775
-
ns
10
340
-
475
-
ns
NOTE:
1. Time required by a device to allow for the indicated function.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
MA
CS
MWR
BUS
tAS
tCS
tWRW
tDS
tDH
CDP1824/3, CDP1824C/3



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