DRV8428PDYYR datasheet(22/46 Pages) TI1

22 / 46 page

DRV8428E, DRV8428P

SLOSE51 – JUNE 2020

www.ti.com

Product Folder Links: DRV8428E DRV8428P

Submit Documentation Feedback

7.3.6.2 Overcurrent Protection (OCP)

An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this

current limit persists for longer than the tOCP time, the FETs in that particular H-bridge are disabled. Once the

OCP condition is removed, normal operation resumes after applying an nSLEEP reset pulse or a power cycling.

7.3.6.3 Thermal Shutdown (OTSD)

If the die temperature exceeds the thermal shutdown limit (TOTSD) all MOSFETs in the H-bridge are disabled.

After the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TOTSD –

THYS_OTSD), normal operation resumes after applying an nSLEEP reset pulse or a power cycling.

Table 7. Fault Condition Summary

FAULT

CONDITION

H-BRIDGE

LOGIC

RECOVERY

VM undervoltage (UVLO)

VM < VUVLO

Disabled

Reset

(VDVDD < 3.6 V)

Automatic: VM > VUVLO

Overcurrent (OCP)

IOUT > IOCP

Disabled

Operating

Latched

Thermal Shutdown (OTSD)

TJ > TTSD

Disabled

Operating

Latched

7.4 Device Functional Modes

7.4.1 Sleep Mode (nSLEEP = 0)

The state of the device is managed by the nSLEEP pin. When the nSLEEP pin is low, the device enters a low-

power sleep mode. In sleep mode, all the internal MOSFETs are disabled. The tSLEEP time must elapse after a

falling edge on the nSLEEP pin before the device enters sleep mode. The device is brought out of sleep

automatically if the nSLEEP pin is brought high. The tWAKE time must elapse before the device is ready for inputs.

7.4.2 Operating Mode (nSLEEP = 1)

When the nSLEEP pin is high, and VM > UVLO, the device enters the active mode. The tWAKE time must elapse

before the device is ready for inputs.

7.4.3 nSLEEP Reset Pulse

A fault can be cleared through a quick nSLEEP pulse. This pulse width must be greater than 20 µs and shorter

than 40 µs. If nSLEEP is low for longer than 40 µs but less than 120 µs, the faults are cleared and the device

may or may not shutdown, as shown in the timing diagram (see Figure 13). This reset pulse does not affect the

status of the charge pump or other functional blocks.

Figure 13. nSLEEP Reset Pulse

Table 8 lists a summary of the functional modes.

Table 8. Functional Modes Summary

CONDITION

CONFIGURATION

H-BRIDGE

DVDD Regulator

Logic

Sleep mode

4.2 V < VM < 33 V

nSLEEP pin = 0

Disabled

Disbaled

Disabled

Operating

4.2 V < VM < 33 V

nSLEEP pin = 1

Operating

DRV8428PDYYR Scheda tecnica(PDF) 22 Page - Texas Instruments

DRV8428PDYYR Scheda tecnica(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Scheda tecnica Scarica

Link URL