PIC24H datasheet(23/290 Pages) MICROCHIP

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Preliminary

DS70175D-page 23

PIC24H

2.4

Arithmetic Logic Unit (ALU)

The PIC24H ALU is 16 bits wide and is capable of addi-

tion, subtraction, bit shifts and logic operations. Unless

otherwise mentioned, arithmetic operations are 2’s

complement in nature. Depending on the operation, the

ALU may affect the values of the Carry (C), Zero (Z),

Negative (N), Overflow (OV) and Digit Carry (DC) Sta-

tus bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W reg-

ister array, or data memory, depending on the address-

ing mode of the instruction. Likewise, output data from

the ALU can be written to the W register array or a data

memory location.

Refer to the “dsPIC30F/33F Programmer’s Reference

Manual” (DS70157) for information on the SR bits

affected by each instruction.

The PIC24H CPU incorporates hardware support for

both multiplication and division. This includes a dedi-

cated hardware multiplier and support hardware for

16-bit divisor division.

2.4.1

MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU

supports unsigned, signed or mixed-sign operation in

several multiplication modes:

16-bit x 16-bit signed

16-bit x 16-bit unsigned

16-bit signed x 5-bit (literal) unsigned

16-bit unsigned x 16-bit unsigned

16-bit unsigned x 5-bit (literal) unsigned

16-bit unsigned x 16-bit signed

8-bit unsigned x 8-bit unsigned

2.4.2

DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

32-bit signed/16-bit signed divide

32-bit unsigned/16-bit unsigned divide

16-bit signed/16-bit signed divide

16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn) and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one cycle per bit of divisor,

so both 32-bit/16-bit and 16-bit/16-bit instructions take

the same number of cycles to execute.

2.4.3

MULTI-BIT DATA SHIFTER

The multi-bit data shifter is capable of performing up to

16-bit arithmetic or logic right shifts, or up to 16-bit left

shifts in a single cycle. The source can be either a

working register or a memory location.

The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the

shift operation. A positive value shifts the operand right.

A negative value shifts the operand left. A value of ‘0’

does not modify the operand.

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