PIC24H datasheet(161/290 Pages) MICROCHIP

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Preliminary

DS70175D-page 161

PIC24H

16.0

INTER-INTEGRATED CIRCUIT

(I2C)

The Inter-Integrated Circuit (I2C) module provides

complete hardware support for both Slave and Multi-

Master modes of the I2C serial communication

standard, with a 16-bit interface.

The PIC24H devices have up to two I2C interface mod-

ules, denoted as I2C1 and I2C2. Each I2C module has

a 2-pin interface: the SCLx pin is clock and the SDAx

pin is data.

Each I2C module ‘x’ (x = 1 or 2) offers the following key

features:

•I2C interface supporting both master and slave

operation.

•I2C Slave mode supports 7 and 10-bit address.

•I2C Master mode supports 7 and 10-bit address.

•I2C port allows bidirectional transfers between

master and slaves.

• Serial clock synchronization for I2C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control).

•I2C supports multi-master operation; detects bus

collision and will arbitrate accordingly.

16.1

Operating Modes

The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

The I2C module can operate either as a slave or a

master on an I2C bus.

The following types of I2C operation are supported:

•I2C slave operation with 7-bit address

•I2C slave operation with 10-bit address

•I2C master operation with 7 or 10-bit address

For details about the communication sequence in each

of these modes, please refer to the “dsPIC30F Family

Reference Manual” (DS70046).

16.2

I2C Registers

I2CxCON and I2CxSTAT are control and status

registers, respectively. The I2CxCON register is

readable and writable. The lower six bits of I2CxSTAT

are read-only. The remaining bits of the I2CSTAT are

read/write.

I2CxRSR is the shift register used for shifting data,

whereas I2CxRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CxRCV is the receive buffer. I2CxTRN is the transmit

operation.

The I2CxADD register holds the slave address. A

status bit, ADD10, indicates 10-bit Address mode. The

I2CxBRG acts as the Baud Rate Generator (BRG)

reload value.

In receive operations, I2CxRSR and I2CxRCV together

form a double-buffered receiver. When I2CxRSR

receives a complete byte, it is transferred to I2CxRCV

and an interrupt pulse is generated.

16.3

I2C Interrupts

The I2C module generates two interrupt flags, MI2CxIF

(I2C Master Events Interrupt Flag) and SI2CxIF (I2C

Slave Events Interrupt Flag). A separate interrupt is

generated for all I2C error conditions.

16.4

Baud Rate Generator

In I2C Master mode, the reload value for the BRG is

located in the I2CxBRG register. When the BRG is

loaded with this value, the BRG counts down to ‘0’ and

stops until another reload has taken place. If clock arbi-

tration is taking place, for instance, the BRG is reloaded

when the SCLx pin is sampled high.

As per the I2C standard, FSCL may be 100 kHz or

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are illegal.

EQUATION 16-1:

SERIAL CLOCK RATE

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

I2CxBRG =

FCY

FSCL

1,111,111

– 1

–

(

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