WM8960CGEFLSLASHV datasheet(65/94 Pages) CIRRUS

65 / 94 page

WM8960

Rev 4.4

12.288

98.304

8.192

3126E8h

11.2896

90.3168

6.947446

F28BD4h

12.288

98.304

7.561846

8FD525h

11.2896

90.3168

6.690133

B0AC93h

12.288

98.304

7.281778

482296h

Table 45 PLL Frequency Examples

WM8960

DACLRC

BCLK

DACDAT

ADCDAT

ADCLRC

MCLK

DAC fs = 48kHz

Bit clock = 3.072MHz

ADC fs = 48kHz

12.288MHz

CLKSEL=0

(PLL not used)

MS=1

(Master mode)

WL=10

(24-bit data)

SYSCLKDIV=0 (Divide by 1)

ADCDIV=000

(Divide by 1)

DACDIV=000

(Divide by 1)

BCLKDIV=0100 (Divide by 4)

Device running in master mode with 24-bit data

MCLK input at 12.288MHz

ADC and DAC running at fs=48kHz

BCLK running at 64fs

WM8960

DACLRC

BCLK

DACDAT

ADCDAT

ADCLRC

MCLK

DAC fs = 48kHz

Bit clock = 3.072MHz

ADC fs = 48kHz

12.288MHz

CLKSEL=0

(PLL not used)

MS=0

(Slave mode)

WL=10

(24-bit data)

SYSCLKDIV=0 (Divide by 1)

ADCDIV=000

(Divide by 1)

DACDIV=000

(Divide by 1)

Device running in slave mode with 24-bit data

MCLK input at 12.288MHz

ADC and DAC running at fs=48kHz

BCLK supplied from host at 64fs in this example

WM8960

DACLRC

BCLK

DACDAT

ADCDAT

ADCLRC

MCLK

DAC fs = 44.1kHz

Bit clock = 2.8224MHz

ADC fs = 8.018kHz

11.2896MHz

CLKSEL=0

(PLL not used)

MS=1

(Master mode)

WL=10

(24-bit data)

SYSCLKDIV=0 (Divide by 1)

ADCDIV=101

(Divide by 5.5)

DACDIV=000

(Divide by 1)

BCLKDIV=0100 (Divide by 4)

Device running in master mode with 24-bit data

MCLK input at 11.2896MHz

ADC running at fs=8.018kHz

DAC running at fs=44.1kHz

BCLK running at 64fs (relative to DAC sample rate, as

DAC is operating at a higher sample rate than ADC)

WM8960

DACLRC

BCLK

DACDAT

ADCDAT

ADCLRC

MCLK

DAC fs = 44.1kHz

Bit clock = 2.8224MHz

ADC fs = 8.018kHz

11.2896MHz

CLKSEL=0

(PLL not used)

MS=0

(Slave mode)

WL=10

(24-bit data)

SYSCLKDIV=0 (Divide by 1)

ADCDIV=101

(Divide by 5.5)

DACDIV=000

(Divide by 1)

Device running in slave mode with 24-bit data

MCLK input at 11.2896MHz

ADC running at fs=8.018kHz

DAC running at fs=44.1kHz

BCLK supplied from host at 64fs in this example (relative

to DAC sample rate, as DAC is operating at a higher

sample rate than ADC)

WM8960

DACLRC

BCLK

DACDAT

ADCDAT

ADCLRC

MCLK

DAC fs = 44.1kHz

Bit clock = 2.8224MHz

ADC fs = 8.018kHz

12MHz

PLLEN=1

(PLL enable)

PLLPRESCALE=0 (Divide by 1)

PLLN=7h

(PLL N value)

PLLK=86C226h

(PLL K value)

SDM=1

(Fractional mode)

CLKSEL=1

(PLL select)

MS=1

(Master mode)

WL=10

(24-bit data)

SYSCLKDIV=2

(Divide by 2)

ADCDIV=101

(Divide by 5.5)

DACDIV=000

(Divide by 1)

BCLKDIV=0100

(Divide by 4)

DCLKDIV=111

(Divide by 16)

Device running in master mode with 24-bit data

MCLK input at 12MHz

PLL Enabled and configured for SYSCLK=11.2896MHz

ADC running at fs=8.018kHz

DAC running at fs=44.1kHz

BCLK running at 64fs (relative to DAC sample rate, as

DAC is operating at a higher sample rate than ADC)

Class D clocks running at 705.6kHz

Table 46 Example Clocking Schemes

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