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STSPIN32F0ATR Scheda tecnica(PDF) 26 Page - STMicroelectronics |
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STSPIN32F0ATR Scheda tecnica(HTML) 26 Page - STMicroelectronics |
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26 / 41 page ![]() Device description STSPIN32F0A 26/41 DocID030766 Rev 2.0 Figure 11: “Standby to normal” operation timing (CREG = 1 µF) Equation 1 ��������������������������������=��������������������������������∙��������������������������������12 ��������������������������������12,������������������������ 6.5 Gate drivers The STSPIN32F0A device integrates a triple half-bridge gate driver able to drive N-channel power MOSFETs or IGBTs. The high-side section is supplied by a bootstrapped voltage technique with an integrated bootstrap diode. All the input lines (refer to Figure 2: "Analog IC block diagram") are connected to a pull- down resistor (60 kΩ typical value) to guarantee the low logic level during the device start-up. The high- and low-side outputs of same half-bridge cannot be simultaneously driven high thanks to an integrated interlocking function. All the input lines of the analog IC have an internal pull-down to guarantee the low logic level during the device start-up and when the MCU lines are not present. |
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