IIS2DLPCTR datasheet(23/69 Pages) STMICROELECTRONICS

23 / 69 page

DocID031788 Rev 4

23/69

IIS2DLPC

Terminology and functionality

3.2.2

Single data conversion on demand mode

The device features a single data conversion on demand mode which is valid for both sets

of operating modes (low-noise disabled or enabled) in the 4 low-power modes. This mode is

enabled by writing the MODE[1:0] bits to '10' in CTRL1 (20h). Low power modes are

selected by writing the LP_MODE[1:0] bits in CTRL1 (20h).

The trigger for output data generation can be managed through the I2C/SPI or by applying a

clock signal on the INT2 pin acting here as an input by writing the SLP_MODE_ SEL bit in

CTRL3 (22h):



When SLP_MODE_SEL = '0', output data generation is triggered by the clock signal on

the INT2 pin (see Figure 5).



When SLP_MODE_SEL = '1', output data generation starts when the SLP_MODE_1

bit is set to '1' logic through the I2C/SPI. When XL data are available in the registers,

this bit is automatically set to '0' and the device is ready for another triggered session.

Output data are generated according to the selected low-power mode.

When output data is saved in an output register or FIFO, the device goes to power-down

mode and waits for a new trigger.

All ODRs in the range from 0 to up to 200 Hz are supported due to the INT2 clock input.

A DRDY signal or FIFO flags are available on the INT1 pin.

Power consumption is the same as that of standard low-power modes for the same ODR.

Figure 5. Single data conversion on demand functionality

At the end of turn-on time T_on, the DRDY interrupt is activated, output data are available to

be read and the device goes into power-down. T_on values depend on the low-power mode

as follows:

T_on (typ.) =



1.20 ms for Low-Power Mode 1



1.70 ms for Low-Power Mode 2



2.30 ms for Low-Power Mode 3



3.55 ms for Low-Power Mode 4

IIS2DLPCTR Scheda tecnica(PDF) 23 Page - STMicroelectronics