R5F566TFGDFP datasheet(3/201 Pages) RENESAS

3 / 201 page

R01DS0315EJ0110 Rev.1.10

Page 3 of 201

Feb 08, 2019

RX66T Group

1. Overview

Operating modes

 Operating modes by the mode-setting pins at the time of release from the reset state

Single-chip mode

Boot mode (SCI interface)

Boot mode (USB interface)

Boot mode (FINE interface)

User boot mode

 Selection of operating mode by register setting

Single-chip mode, user boot mode, On-chip ROM disabled extended mode,

On-chip ROM enabled extended mode

 Endian selectable

Clock

Clock generation circuit

 Main clock oscillator, low-speed/high-speed on-chip oscillator, PLL frequency

synthesizer, and IWDT-dedicated on-chip oscillator

 The peripheral module clocks can be set to frequencies above that of the system clock.

 Main-clock oscillation stoppage detection

 Separate frequency-division and multiplication settings for the system clock (ICLK),

peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and

external bus clock (BCLK)

The CPU and other bus masters run in synchronization with the system clock (ICLK): Up

to 160 MHz

Peripheral modules of MTU3 (Internal peripheral bus), GPTW (Internal peripheral bus),

HRPWM (Internal peripheral bus), RSPI, and SCI11 run in synchronization with PCLKA,

which operates at up to 120 MHz.

Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz

MTU3 (counter reference clocks), GPTW (counter reference clocks), and HRPWM

(reference clocks) are synchronized with PCLKC: Up to 160 MHz

ADCLK in the S12AD runs in synchronization with PCLKD: Up to 60 MHz

Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz

Devices connected to the external bus run in synchronization with the external bus clock

(BCLK): Up to 40 MHz

 Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a

reference clock of the PLL circuit

Reset

Nine types of reset

 RES# pin reset: Generated when the RES# pin is driven low.

 Power-on reset: Generated when the RES# pin is driven high and VCC rises.

 Voltage-monitoring 0 reset: Generated when VCC falls.

 Voltage-monitoring 1 reset: Generated when VCC falls.

 Voltage-monitoring 2 reset: Generated when VCC falls.

 Deep software standby reset: Generated in response to an interrupt to trigger release

from deep software standby.

 Independent watchdog timer reset: Generated when the independent watchdog timer

underflows, or a refresh error occurs.

 Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh error

occurs.

 Software reset: Generated by register setting.

Power-on reset

If the RES# pin is at the high level when power is supplied, an internal reset is generated.

After VCC has exceeded the voltage detection level and the specified period has elapsed,

the reset is cancelled.

Voltage detection circuit (LVDA)

Monitors the voltage being input to the VCC pin and generates an internal reset or internal

interrupt.

 Voltage detection circuit 0

Capable of generating an internal reset

The option-setting memory can be used to select enabling or disabling of the reset.

Voltage detection level: Selectable from two different levels

 Voltage detection circuits 1 and 2

Voltage detection level: Selectable from five different levels

Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)

Capable of generating an internal reset

 Two types of timing are selectable for release from reset

An internal interrupt can be requested.

 Detection of voltage rising above and falling below thresholds is selectable.

 Maskable or non-maskable interrupt is selectable

Voltage detection monitoring

Event linking

Table 1.1

Outline of Specifications (2/9)

Classification

Module/Function

Description

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