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R5F566TFGDFP Scheda tecnica(PDF) 1 Page - Renesas Technology Corp

Il numero della parte R5F566TFGDFP
Spiegazioni elettronici  160-MHz, 32-bit RX MCU, on-chip FPU, 928 CoreMark, Supportive of 5V power supply,
PDF  201 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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RX66T Group
Renesas MCUs
Datasheet
R01DS0315EJ0110 Rev.1.10
Page 1 of 201
Feb 08, 2019
Features
■ 32-bit RXv3 CPU core
 Maximum operating frequency: 160 MHz
Capable of 928 CoreMark in operation at 160 MHz
 JTAG and FINE (one-line) debugging interfaces
■ Low-power design and architecture
 Operation from a single 2.7- to 5.5-V supply
 Four low-power modes
■ On-chip code flash memory
 Supports versions with 1 Mbytes/512 Kbytes/256 Kbytes
 No wait cycles at up to 120 MHz or when the ROM cache is hit
 User code is programmable by on-board or off-board programming.
■ On-chip data flash memory
 32 Kbytes, reprogrammable up to 100,000 times
 Programming/erasing as background operations (BGOs)
■ On-chip SRAM, no wait states
 128K/64 Kbytes of SRAM (no wait states)
 16 Kbytes of RAM with ECC (with wait)
■ Data transfer
 DMACa: 8 channels
 DTCa: 1 channel
■ ELC
 Module operation can be initiated by event signals without using
interrupts
 Linked operation between modules is possible when the CPU is in
sleep mode
■ Reset and supply management
 Power-on reset (POR)
 Low voltage detection (LVDA) with voltage settings
■ Clock functions
 Frequency of resonator for main clock oscillator: 8 to 24 MHz (this
can be used as the PLL reference clock)
 High-speed on-chip oscillator: 16 MHz/18 MHz/20 MHz (this can
be used as the PLL reference clock)
 Low-speed on-chip oscillator: 240 kHz
■ Independent watchdog timer
 120-kHz IWDT-dedicated on-chip oscillator clock operation
■ Useful functions for IEC60730 compliance
 Oscillation-stoppage detection, functions for self-diagnosis and
detection of disconnection for the A/D converter, clock frequency
accuracy measurement circuit, independent watchdog timer, RAM
test-assisting function by DOC, and CRCA, etc.
 Register write protection function can protect values in important
registers against overwriting.
■ External bus
 Bus clock at 40 MHz (max)
 Four CS areas
 8- or 16-bit bus space is selectable per area
■ Various communications interfaces
 Host/function or OTG controller (1 channel) with full-speed USB
2.0 (USBb) transfer
 CAN (compliant with ISO11898-1), incorporating 32 mailboxes
(1 channel)
 SCIj and SCIh with multiple functionalities (up to 6 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I2C, and
extended serial mode.
 SCIi with 16-byte transmission and reception FIFOs (1 channel)
 I2C bus interface (RIICa) for transfer at up to 400 kbps (fast mode),
capable of SMBus operation (1 channel)
 RSPId (1 channel) for transfer at up to 30 Mbps
■ Up to 31 extended-function timers
 32-bit GPTW (10 channels): operation at 160 MHz, input capture,
output compare, PWM waveforms: 10 output channels in single-
phase complementary PWM mode/3 output channels in 3-phase
complementary PWM mode/2 output channels in 5-phase
complementary PWM mode, phase-counting mode, linkage with
comparator (counting operation, PWM negate control)
 16-bit MTU3d (9 channels): operation at 160 MHz, input capture,
output compare, PWM waveforms: 2 output channels in 3-phase
complementary PWM mode, phase-counting mode
 8-bit TMR (8 channels)
 16-bit CMT (4 channels)
■ High-resolution PWM waveform generation circuit
(HRPWM): 4 channels
 Controlling the timing of rising or falling of the PWM output
waveform for 32-bit GPTW is realized with minimum of 195 ps
resolution (in operation at 160 MHz)
■ 12-bit A/D converter (S12ADH):
total of 30 channels for three units
 Up to three 12-bit units of sample-and-hold circuit included
Unit 0 (8 channels for 3 sample-and-hold circuits),
Unit 1 (8 channels for 3 sample-and-hold circuits),
Unit 2 (14 channels)
 Programmable gain amplifier with pseudo differential amplification
(3 channels × 2)
■ Analog Comparator (CMPC): 6 channels
■ 12-bit D/A converter: 2 channels
 Usable as a reference voltage for the analog comparator
■ Temperature sensor for measuring temperature
within the chip
■ Encryption functions (Trusted Secure IP Lite)
 128- or 256-bit key length of AES for ECB, CBC, GCM, others
 True random number generator
 Unauthorized access to the encryption engine is disabled and
imposture and falsification of information are prevented
 Safe management of keys
■ Up to 110 pins for general I/O ports
 5-V tolerance, open drain, input pull-up, switchable driving ability
■ Recommended operating temp. range (Topr)
 –40C to +85C
 –40C to +105C
PLQP0144KA-B 20 × 20 mm, 0.5 mm pitch
PLQP0112JA-B 20 × 20 mm, 0.65 mm pitch
PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch
PLQP0080JA-A 14 × 14 mm, 0.65 mm pitch
PLQP0080KB-B 12 × 12 mm, 0.5 mm pitch
PLQP0064KB-B 10 × 10 mm, 0.5 mm pitch
160-MHz, 32-bit RX MCU, on-chip FPU, 928 CoreMark, Supportive of 5V power supply,
up to 1-MB flash memory, up to 128-KB SRAM, 32-KB data flash memory, 16-KB SRAM with ECC, Simultaneous sampling with
3 units of 12-bit A/D converter (up to 7 channels), Single-end/pseudo differential input supportive amplifier (6 channels),
Analog comparator (6 channels), 160 MHz PWM (4 channels for 3-phase complementary, 2 channels for 5-phase
complementary, 10 channels for single-phase complementary), 4-channel high-resolution PWM with resolution of 195 ps at the
minimum, Host/function or OTG controller with full-speed USB 2.0 transfer, CAN, Encryption functions (optional)
R01DS0315EJ0110
Rev.1.10
Feb 08, 2019
Features


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