STM32F334C8U6TR datasheet(87/125 Pages) STMICROELECTRONICS

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DS9994 Rev 9

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STM32F334x4 STM32F334x6 STM32F334x8

Electrical characteristics

103

SPI characteristics

Unless otherwise specified, the parameters given in Table 53 for SPI are derived from tests

performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions

summarized in Table 19: General operating conditions.

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 62. I2C analog filter characteristics(1)

Symbol

Parameter

Min.

Max.

Unit

tAF

Maximum pulse width of spikes that are

suppressed by the analog filter.

50(2)

260(3)

1. Guaranteed by design, not tested in production.

2. Spikes with width below tAF(min.) are filtered.

3. Spikes with width above tAF(max.) are not filtered.

Table 63. SPI characteristics(1)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode 2.7 < VDD < 3.6 V

MHz

Master mode 2 < VDD < 3.6 V

Slave mode 2 < VDD < 3.6 V

Slave mode transmitter/full

duplex

2 < VDD < 3.6 V

18(2)

DuCy(SCK)

Duty cycle of SPI clock

frequency

Slave mode

tsu(NSS)

NSS setup time

Slave mode, SPI presc = 2

4*Tpclk

th(NSS)

NSS hold time

Slave mode, SPI presc = 2

2*Tpclk

tw(SCKH)

tw(SCKL)

SCK high and low time

Master mode

Tpclk-2

Tpclk

Tpclk+2

tsu(MI)

Data input setup time

Master mode

tsu(SI)

Slave mode

th(MI)

Data input hold time

Master mode

th(SI)

Slave mode

ta(SO)

Data output access time

Slave mode

tdis(SO)

Data output disable time

Slave mode

tv(SO)

Data output valid time

Slave mode 2.7 < VDD < 3.6 V

Slave mode 2 < VDD < 3.6 V

27.5

tv(MO)

Master mode

1.5

th(SO)

Data output hold time

Slave mode

7.5

th(MO)

Master mode

1. Data based on characterization results, not tested in production.

2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low

or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having tsu(MI) = 0 while Duty(SCK) = 50%.

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