TMS320F28375DPZP datasheet(66/226 Pages) TI

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8.9.3.2.2 Internal Clock Frequencies

Section 8.9.3.2.2.1 provides the clock frequencies for the internal clocks.

8.9.3.2.2.1 Internal Clock Frequencies

MIN

NOM

MAX

UNIT

f(SYSCLK)

Frequency, device (system) clock

200(2)

MHz

tc(SYSCLK)

Period, device (system) clock

5(2)

500

f(PLLRAWCLK)

Frequency, system PLL output (before SYSCLK

divider)

120

400

MHz

f(AUXPLLRAWCLK)

Frequency, auxiliary PLL output (before AUXCLK

divider)

120

400

MHz

f(AUXPLL)

Frequency, AUXPLLCLK

MHz

f(PLL)

Frequency, PLLSYSCLK

200(2)

MHz

f(LSP)

Frequency, LSPCLK

200(2)

MHz

tc(LSPCLK)

Period, LSPCLK

5(2)

500

f(OSCCLK)

Frequency, OSCCLK (INTOSC1 or INTOSC2 or

XTAL or X1)

See respective clock

MHz

f(EPWM)

Frequency, EPWMCLK(1)

100

MHz

f(HRPWM)

Frequency, HRPWMCLK

100

MHz

(1)

For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

(2)

Using an external clock source. If INTOSC1 or INTOSC2 is used as the clock source, then the maximum frequency is 194 MHz and

the minimum period is 5.15 ns.

8.9.3.2.3 Output Clock Frequency and Switching Characteristics

Section 8.9.3.2.3.1 provides the frequency of the output clock. Section 8.9.3.2.3.2 shows the switching

characteristics of the output clock, XCLKOUT.

8.9.3.2.3.1 Output Clock Frequency

MIN

MAX

UNIT

f(XCO)

Frequency, XCLKOUT

MHz

8.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)

over recommended operating conditions (unless otherwise noted)

PARAMETER(1) (2)

MIN

MAX

UNIT

tf(XCO)

Fall time, XCLKOUT

tr(XCO)

Rise time, XCLKOUT

tw(XCOL)

Pulse duration, XCLKOUT low

H – 2

H + 2

tw(XCOH)

Pulse duration, XCLKOUT high

H – 2

H + 2

(1)

A load of 40 pF is assumed for these parameters.

(2)

H = 0.5tc(XCO)

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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