TMS320F28375DPZP datasheet(103/226 Pages) TI

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8.10.1.2 ADC Electrical Data and Timing

Section 8.10.1.2.1 shows the ADC operating conditions for 16-bit differential mode. Section 8.10.1.2.2 shows the

ADC characteristics for 16-bit differential mode. Section 8.10.1.2.3 shows the ADC operating conditions for 12-

bit single-ended mode. Section 8.10.1.2.4 shows the ADC characteristics for 12-bit single-ended mode. Section

8.10.1.2.5 shows the ADCEXTSOC timing requirements.

8.10.1.2.1 ADC Operating Conditions (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)

MIN

TYP

MAX

UNIT

ADCCLK (derived from PERx.SYSCLK)

MHz

Sample window duration (set by ACQPS and PERx.SYSCLK)(1)

320

VREFHI

2.4

2.5 or 3.0

VDDA

VREFLO

VSSA

VREFHI – VREFLO

2.4

VDDA

ADC input conversion range

VREFLO

VREFHI

ADC input signal common mode voltage(2) (3)

VREFCM – 50

VREFCM

VREFCM + 50

(1)

The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

(2)

VREFCM = (VREFHI + VREFLO)/2

(3)

The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO.

Note

The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this

level, the VREF internal to the device may be disturbed, which can impact results for other ADC or

DAC inputs using the same VREF.

Note

The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI

pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V

internally, giving improper ADC conversion or DAC output.

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TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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