LTM4656 datasheet(21/28 Pages) AD

21 / 28 page

LTM4656/LTM4656-1

Rev. 0

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• Do not put via directly on the pad, unless they are

capped or plated over.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

• For parallel modules, tie the VFB, COMP,SS, and SDHN

pins together. Use an internal layer to closely connect

these pins together. The TRACK pin can be tied a com-

mon capacitor for regulator soft-start.

• Bring out test points on the signal pins for monitoring.

Figure18givesagoodexampleoftherecommendedlayout.

the difference of 40°C divided by 4.48W equals a 9°C/W

θJA thermal resistance. Table 2 specifies a 10°C/W value

which is very close. Table 2, Table 3, and Table 4 provide

equivalent thermal resistances for 12V, 24V and 36V out-

putswithandwithoutairflowandheatsinking.Thederived

thermal resistances in Table 2 to Table 4 for the various

conditions can be multiplied by the calculated power loss

asafunctionofambienttemperaturetoderivetemperature

rise above ambient, thus maximum junction temperature.

Room temperature power loss can be derived from the ef-

ficiency curves in the Typical Performance Characteristics

section and adjusted with the above ambient temperature

multiplicative factors. The printed circuit board is a 1.6mm

thick four-layer board with two-ounce copper for the two

outer layers and one-ounce copper for the two inner lay-

ers. The PCB dimensions are 95mm × 76mm.

SAFETY CONSIDERATIONS

The LTM4656 modules do not provide galvanic isolation

from VIN to VOUT. There is no internal fuse. The device

does support thermal shutdown and overcurrent protec-

tion with retry. If required, a slow blow fuse with a rating

twice the maximum input current needs to be provided to

protect each unit from catastrophic failure.

LAYOUT CHECKLIST/EXAMPLE

The high integration of LTM4656 makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

• Use large PCB copper areas for high current paths,

includingVIN,BVINGNDandVOUT.Ithelpstominimize

the PCB conduction loss and thermal stress.

• Placehighfrequencyceramicinputandoutputcapaci-

tors next to the BVIN, PGND and VOUT pins to minimize

high frequency noise.

• Place a dedicated power ground layer underneath

the unit.

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

APPLICATIONS INFORMATION

Figure 18. Recommended PCB Layout

4656 F18

OPTIONAL INPUT CAP

VIN

SENSE

GND

VOUT

BVIN

(a) TOP LAYER: LTM4656 16mm × 16mm

BVIN CAPS

4656 F18

VIN

SENSE

GND

VOUT

BVIN

(b) BOTTOM LAYER: LTM4656 16mm × 16mm

BVIN CAPS

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