MC56F81663 datasheet(11/73 Pages) NXP

11 / 73 page

• Separate I2C slave registers to minimize software overhead because of master/slave

switching

• Support for 7-bit or 10-bit addressing, address range, SMBus alert and general call

address

• Transmit data register that supports interrupt or DMA requests

• Receive data register that supports interrupt or DMA requests

• Software-controllable ACK or NACK, with optional clock stretching on ACK/

NACK bit

• Configurable clock stretching, to avoid transmit FIFO underrun and receive FIFO

overrun errors

• Flag and optional interrupt at end of packet, STOP condition, or bit error detection

1.5.13 Windowed Computer Operating Properly (COP) watchdog

• Programmable windowed timeout period

• Support for operation in all power modes: run mode, wait mode, stop mode

• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is

detected

• Selectable reference clock source in support of EN60730 and IEC61508

• Selectable clock sources:

• External crystal oscillator

• On-chip low-power 200 kHz oscillator

• System bus (IPBus up to 50 MHz)

• 8 MHz / 2 MHz IRC

• Support for interrupt generation

1.5.14 External Watchdog Monitor (EWM)

• Monitors external circuit as well as the software flow

• Programmable timeout period

• Interrupt capability prior to timeout

• Independent output (EWM_OUT_b) that places external circuit (but not CPU and

peripheral) in a safe mode when EWM timeout occurs

• Selectable reference clock source in support of EN60730 and IEC61508

• Wait mode and Stop mode operation is not supported.

• Selectable clock sources:

• External crystal oscillator

• On-chip low-power 200 kHz oscillator

• System bus (IPBus up to 50 MHz)

• 8 MHz / 2 MHz IRC

Peripheral highlights

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 Scheda tecnica(PDF) 11 Page - NXP Semiconductors