EM78P152S datasheet(34/52 Pages) ETC1

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EM78P152/3S

8-Bit Microcontroller with OTP ROM

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Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

5.13 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and one

or more operands. Normally, all instructions are executed within one single instruction

cycle (one instruction consists of two oscillator periods), unless the program counter is

changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or

logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2",

⋅⋅⋅⋅). In this case, the

execution takes two instruction cycles.

If for some reasons, the specification of the instruction cycle is not suitable for certain

applications, try modifying the instruction as follows:

A) Modify one instruction cycle to consist of four oscillator periods.

B) "JMP," "CALL," "RET," "RETL," "RETI," or the conditional skip ("JBS," "JBC," "JZ,"

"JZA," "DJZ,” "DJZA") commands which were tested to be true, are executed within

two instruction cycles. The instructions that are written to the program counter also

take two instruction cycles.

Case (A) is selected by the Code Option bit, called CLK. One instruction cycle consists

of two oscillator clocks if CLK is low; and four oscillator clocks if CLK is high.

Note that once the four oscillator periods within one instruction cycle is selected as in

Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc/2.

Moreover, the instruction set has the following features:

1) Every bit of any register can be set, cleared, or tested directly.

2) The I/O register can be regarded as general register. That is, the same instruction

can operate on I/O register.

The following symbols are used in the Instruction Set table:

Convention:

= Register designator that specifies which one of the registers (including operation and general purpose

registers) is to be utilized by the instruction.

Bits 6 and 7 in R4 determine the selected register bank.

= Bit field designator that selects the value for the bit located in the register R and which affects the

operation.

= 8 or 10-bit constant or literal value

Binary Instruction

Hex

Mnemonic

Operation

Status Affected

0 0000 0000 0000

0000

NOP

No Operation

None

0 0000 0000 0001

0001

DAA

Decimal Adjust A

0 0000 0000 0010

0002

CONTW

→ CONT

None

0 0000 0000 0011

0003

SLEP

→ WDT, Stop oscillator

T, P

0 0000 0000 0100

0004

WDTC

→ WDT

T, P

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