ACE25AB400G

Serial NOR Flash Memory 4M bits 3.0V Dual I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

10

Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable

command sequence: CS# goes low→Sending the Write Disable command→CS# goes high. The WEL bit

is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program,

Sector Erase, Block Erase and Chip Erase commands.

Read Status Register (RDSR) (05H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may

be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one

of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending

a new command to the device. It is also possible to read the Status Register continuously.

Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Be-

fore it can be accepted, a Write Enable (WREN) command must previously have been executed. After the

Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch

(WEL).

The Write Status Register (WRSR) command has no effect on S6, S5, S4, S1 and S0 of the Status

Register. CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write

Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write

Status Register cycle (whose duration is tw) is initiated. While the Write Status Register cycle is in

progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write

In Progress (WIP) bit is 1 during the self- timed Write Status Register cycle, and is 0 when it is completed.

When the cycle is completed, the Write Enable Latch (WEL) is reset.

Figure3. Write Disable Sequence Diagram

Figure4. Read Status Register Sequence Diagram