ACE25AB400GFMLTH datasheet(11/37 Pages) ACE

11 / 37 page

ACE25AB400G

Serial NOR Flash Memory 4M bits 3.0V Dual I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect

(BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1.0.

The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP) bit, the Write

Status Register (WRSR) command allows the user to set the Status Register Write Disable (SRWD) bit to

1. The Status Register Write Disable (SRWD) bit allow the device to be put in another Software Protected

Mode. Once the SRWD bit is set to 1, the Write Status Register (WRSR) command is not executed, and

the Block Protect bits (BP1, BP0) are read only.

Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO,

each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte

addressed can be at any location. The address is automatically incremented to the next higher address

after each byte of data is shifted out. Therefore, the whole memory can be read with a single Read Data

Bytes (READ) command. During an Erase, Program or Write cycle, Read Data Byte (READ) command

will be rejected without affecting the cycle in progress.

Figure5. Write Status Register Sequence Diagram

Figure6. Read Data Bytes Sequence Diagram

ACE25AB400GFMLTH Scheda tecnica(PDF) 11 Page - ACE Technology Co., LTD.