PIMXRT406LCAF4A datasheet(67/71 Pages) NXP

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Revision history

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

Revision history

Table 60 provides a revision history for this data sheet.

Table 60. i.MX RT1015 data sheet document revision history

Rev. Number

Date

Substantive Change(s)

Rev. 2

03/2021

• Updated the M7 Core and external memory descriptions in the Section 1.1, Features

• Updated the Figure 1, "Part number nomenclature—i.MX RT10XX family"

• Updated the frequency of RTC OSC and baud rates of LPUART in the Table 2, i.MX

RT1015 modules list

• Updated the descriptions about TEST_MODE in the Table 3, Special signal

considerations

• Added system and bus frequencies in the Table 9, Operating ranges

• Updated the test conditions and max current of DCDC_IN in the Table 11, Maximum

supply currents

• Added a note in the Section 4.2.1.1, Power-up sequence

• Updated the value of reference clock in the Table 16, Ethernet PLL’s electrical

parameters

• Added the high-level and low-level output current in the Table 20, Single voltage GPIO

DC parameters

• Added a footnote for GPIO_EMC_04 in the Table 59, 14 x 14 mm functional contact

assignments

Rev. 1

04/2019

• Updated the SNVS descriptions in the Table 2, i.MX RT1015 modules list

• Updated the Section 4.8.1, LPSPI timing parameters

Rev. 0.1

03/2019

• Added audio information in the Section 1, i.MX RT1015 introduction

• Updated FlexPWMs and Quadrature Encoder/Decoder in the Section 1.1, Features

• Updated the Table 1, Ordering information

• Updated keypad and GP timer numbers in the Figure 2, "i.MX RT1015 system block

diagram"

• Changed keypad to 4 x 4 in the Table 2, i.MX RT1015 modules list

• Removed the USB OTG2 from the Table 2, i.MX RT1015 modules list, Table 7, Absolute

maximum ratings, and Section 4.2.1.1, Power-up sequence

• Updated on-chip termination information for the JTAG_TCK and JTAG_MOD in the

Table 4, JTAG controller interface summary

• Updated descriptions in the Section 4.2.2.2.3, LDO_USB

• Changed the 528 MHz PLL to System PLL in the Table 15, System PLL’s electrical

parameters

• Changed the 480 MHz PLL to USB PLL in the Table 17, USB PLL’s electrical

parameters

Rev. 0

01/2019

• Initial version

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